_primary.vhd

来自「用VHDL设计具有简单MIPS功能的源码」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity MIPS is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        D_NPC           : out    vl_logic_vector(31 downto 0);
        D_IR            : out    vl_logic_vector(31 downto 0);
        ALUResult       : out    vl_logic_vector(31 downto 0);
        MEMDataOut      : out    vl_logic_vector(31 downto 0)
    );
end MIPS;