_primary.vhd

来自「利用verilog实现单片机的反向设计。编程环境为modelsim6.0」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity divide is
    port(
        src1            : in     vl_logic_vector(7 downto 0);
        src2            : in     vl_logic_vector(7 downto 0);
        des1            : out    vl_logic_vector(7 downto 0);
        des2            : out    vl_logic_vector(7 downto 0);
        desOv           : out    vl_logic
    );
end divide;