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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity \CLKLOCK\ is
generic(
\CLOCKBOOST\ : integer := 1;
\INPUT_FREQUENCY\: real := 50.000000;
\TPD\ : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);
uart.jhd
MODULE uart DEFIN ..\..\..\uart_verilog\uart.v
SUBMODULE txmit
INSTANCE u2
SUBMODULE rcvr
INSTANCE u1
uart_v.syn
JDF B
// Created by Version 6.1
PROJECT uart_v
DESIGN uart_v Normal
DEVKIT LFXP3C-3T100C
ENTRY Pure Verilog HDL
MODULE ..\..\..\uart_verilog\uart.v
MODSTYLE uart Normal
MODULE ..\..\..\uart_v