uart_v.syn

UART 串口程序

JDF B
// Created by Version 6.1 
PROJECT uart_v
DESIGN uart_v Normal
DEVKIT LFXP3C-3T100C
ENTRY Pure Verilog HDL
MODULE ..\..\..\uart_verilog\uart.v
MODSTYLE uart Normal
MODULE ..\..\..\uart_verilog\rcvr.v
MODSTYLE rcvr Normal
TESTFIXTURE rcvr ..\..\..\uart_verilog\rcvr_tf.v
MODULE ..\..\..\uart_verilog\txmit.v
MODSTYLE txmit Normal
TESTFIXTURE txmit ..\..\..\uart_verilog\txmit_tf.v
SYNTHESIS_TOOL Synplify
TOPMODULE uart