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library verilog; use verilog.vl_types.all; entity sub4 is port( \in\ : in vl_logic_vector(31 downto 0); \out\ : out vl_logic_vector(31 downto 0) );

library verilog; use verilog.vl_types.all; entity mux24 is port( i0 : in vl_logic_vector(3 downto 0); i1 : in vl_logic_vector(3 downto 0);

library verilog; use verilog.vl_types.all; entity sum4 is port( s : out vl_logic_vector(3 downto 0); p : in vl_logic_vector(3 downto 0);

Analysis & Synthesis report for test Wed Apr 22 21:04:05 2009 Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version --------------------- ; Table of Contents ; ---------------------

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

library verilog; use verilog.vl_types.all; entity spi_slave_model is generic( tp : integer := 1 ); port( rst : in vl_logic; ss

library verilog; use verilog.vl_types.all; entity glbl is generic( roc_width : integer := 100000; toc_width : integer := 0 ); end glbl;

verilog work i2c_master_bit_ctrl.v verilog work i2c_master_byte_ctrl.v verilog work i2c_master_top.v

Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version 38 2277 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Sta

Version 7.2 Build 151 09/26/2007 SJ Full Version 11 1009 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Path