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library verilog; use verilog.vl_types.all; entity exp is port( clk : in vl_logic; reset : in vl_logic; dds_out : out vl_logic_vecto

library verilog; use verilog.vl_types.all; entity sum7 is port( s : out vl_logic_vector(6 downto 0); p : in vl_logic_vector(6 downto 0);

library verilog; use verilog.vl_types.all; entity sub4 is port( \in\ : in vl_logic_vector(31 downto 0); \out\ : out vl_logic_vector(31 downto 0) );

library verilog; use verilog.vl_types.all; entity decoder is port( \in\ : in vl_logic_vector(31 downto 0); sel : in vl_logic; o0

library verilog; use verilog.vl_types.all; entity add4 is port( \in\ : in vl_logic_vector(31 downto 0); \out\ : out vl_logic_vector(31 downto 0) );

library verilog; use verilog.vl_types.all; entity mux8 is port( i0 : in vl_logic_vector(31 downto 0); i1 : in vl_logic_vector(31 downto 0);

library verilog; use verilog.vl_types.all; entity mux2 is port( i0 : in vl_logic_vector(31 downto 0); i1 : in vl_logic_vector(31 downto 0);

library verilog; use verilog.vl_types.all; entity arm7 is port( nOPC : out vl_logic; nCPI : out vl_logic; CPA : in vl_logic;

library verilog; use verilog.vl_types.all; entity mux4 is port( i0 : in vl_logic_vector(31 downto 0); i1 : in vl_logic_vector(31 downto 0);

library verilog; use verilog.vl_types.all; entity mux24 is port( i0 : in vl_logic_vector(3 downto 0); i1 : in vl_logic_vector(3 downto 0);