vopta5rsb4

ARM10 INSTALALTION GUIDE

library verilog;
use verilog.vl_types.all;
entity sub4 is
    port(
        \in\            : in     vl_logic_vector(31 downto 0);
        \out\           : out    vl_logic_vector(31 downto 0)
    );
end sub4;