voptryfdn8

来自「ARM10 INSTALALTION GUIDE」· 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity mux24 is
    port(
        i0              : in     vl_logic_vector(3 downto 0);
        i1              : in     vl_logic_vector(3 downto 0);
        sel             : in     vl_logic;
        \out\           : out    vl_logic_vector(3 downto 0)
    );
end mux24;