_primary.vhd

来自「用Verilog 编写的8位risc cpu」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity exp is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        dds_out         : out    vl_logic_vector(7 downto 0);
        expdin          : out    vl_logic_vector(7 downto 0);
        expdout         : in     vl_logic_vector(7 downto 0);
        expaddr         : in     vl_logic_vector(6 downto 0);
        expread         : in     vl_logic;
        expwrite        : in     vl_logic
    );
end exp;