代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/359174/10162680
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/163111/10175060
mpf i2c_slave.mpf
;
; Copyright Model Technology, a Mentor Graphics Corporation company 2003,
; All rights reserved.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../ver
www.eeworm.com/read/356809/10221008
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ShiftRegController is
port(
Clock50MHz : in vl_logic;
BitStreamIn : in vl_logic;
SampleCLKfromDM : in
www.eeworm.com/read/356716/10222442
makefile
#
# PacoBlaze Makefile
#
# Path for the Xilinx sources
XILINX = ../xilinx
# Xilinx implementation of PicoBlaze
KCPSM2 = $(XILINX)/kcpsm2.v
KCPSM3 = $(XILINX)/kcpsm3.v
UNISIMS = $(wildcard
www.eeworm.com/read/162707/10280604
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity counter_4 is
port(
clk : in vl_logic;
reset : in vl_logic;
ce : in vl_logic
www.eeworm.com/read/162707/10280611
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity comparator_4 is
port(
clk : in vl_logic;
reset : in vl_logic;
a : in vl_lo
www.eeworm.com/read/162707/10280619
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity shift is
port(
clk : in vl_logic;
din : in vl_logic;
dout : out vl_logic_vec
www.eeworm.com/read/162707/10280671
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ex2 is
port(
a : in vl_logic;
d : out vl_logic
);
end ex2;
www.eeworm.com/read/162707/10280678
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity d_flip_flop is
port(
clk : in vl_logic;
reset : in vl_logic;
din : in vl_log
www.eeworm.com/read/280359/10335502
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult is
port(
clock : in vl_logic;
dataa : in vl_logic_vector(15 downto 0);
datab :