_primary.vhd

来自「实现一个FIR滤波器」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity mult is
    port(
        clock           : in     vl_logic;
        dataa           : in     vl_logic_vector(15 downto 0);
        datab           : in     vl_logic_vector(8 downto 0);
        result          : out    vl_logic_vector(24 downto 0)
    );
end mult;