代码搜索：Verilog

找到约 10,000 项符合「Verilog」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/320069/13433249

bak part2.qsf.bak

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/320069/13433324

bak part3.qsf.bak

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/320069/13433403

bak part4.qsf.bak

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/320069/13433546

qsf part1.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/319407/13452216

vif reg_counter.vif

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file reg_
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www.eeworm.com/read/302855/13826194

qsf fir1.qsf

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/302855/13826256

qsf fir2.qsf

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/221706/6295989

qmsg clock.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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www.eeworm.com/read/492763/6408695

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity uart_txd_vlg_vec_tst is end uart_txd_vlg_vec_tst;
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www.eeworm.com/read/490774/6442296

qmsg adc.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
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