reg_counter.vif

程序补充说明：时钟输入：在每个时钟的正沿或负沿对数据进行处理。时钟的正沿有效还是负沿有效

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  reg_counter.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Xilinx

# RTL and technology files
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original -verilog ../reg_counter.v
vif_set_top_module -original -top reg_counter
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog reg_counter.vm
vif_set_top_module -translated -top reg_counter 
# Read FSM encoding

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies

# Technology sequential redundancies

# Inversion map points

# Port mappping and directions

# Black box mapping


# Other sequential cells, including multidimensional arrays

# Constant Registers

# Retimed Registers