adc.map.qmsg

对AD0809进行操作

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 24 14:44:33 2009 " "Info: Processing started: Sun May 24 14:44:33 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ADC.v(132) " "Warning (10273): Verilog HDL warning at ADC.v(132): extended using \"x\" or \"z\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 132 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ADC.v(66) " "Warning (10268): Verilog HDL information at ADC.v(66): always construct contains both blocking and non-blocking assignments" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 66 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADC.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ADC.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADC " "Info: Found entity 1: ADC" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ADC " "Info: Elaborating entity \"ADC\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|ADC\|state 6 " "Info: State machine \"\|ADC\|state\" contains 6 states" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|ADC\|state " "Info: Selected Auto state machine encoding method for state machine \"\|ADC\|state\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|ADC\|state " "Info: Encoding result for state machine \"\|ADC\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.st5 " "Info: Encoded state bit \"state.st5\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.st4 " "Info: Encoded state bit \"state.st4\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.st3 " "Info: Encoded state bit \"state.st3\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.st2 " "Info: Encoded state bit \"state.st2\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.st1 " "Info: Encoded state bit \"state.st1\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.st0 " "Info: Encoded state bit \"state.st0\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ADC\|state.st0 000000 " "Info: State \"\|ADC\|state.st0\" uses code string \"000000\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ADC\|state.st1 000011 " "Info: State \"\|ADC\|state.st1\" uses code string \"000011\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ADC\|state.st2 000101 " "Info: State \"\|ADC\|state.st2\" uses code string \"000101\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ADC\|state.st3 001001 " "Info: State \"\|ADC\|state.st3\" uses code string \"001001\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ADC\|state.st4 010001 " "Info: State \"\|ADC\|state.st4\" uses code string \"010001\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ADC\|state.st5 100001 " "Info: State \"\|ADC\|state.st5\" uses code string \"100001\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0}  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.map.smsg " "Info: Generated suppressed messages file F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "48 " "Info: Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Peak virtual memory: 159 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 24 14:44:37 2009 " "Info: Processing ended: Sun May 24 14:44:37 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}