代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/281017/10272381
qmsg eeprom.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/162707/10280659
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ex1 is
port(
a : in vl_logic;
b : in vl_logic;
c : in vl_logic;
www.eeworm.com/read/162707/10280665
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity full_adder is
port(
a : in vl_logic;
b : in vl_logic;
cin : in vl_logi
www.eeworm.com/read/425799/10321610
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mt48lc8m16a2 is
generic(
addr_bits : integer := 12;
data_bits : integer := 16;
col_bits : integer := 9;
www.eeworm.com/read/424880/10403924
scr run_sim.scr
#!/bin/csh -f
# GLOBAL VARIABLES
###################
set sim_top = testbench;
set arg_tool = "NCSim"; # By default NCSim is used as simulation tool
set arg_wave = 0; # By defa
www.eeworm.com/read/353518/10441903
qsf d_agc.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/352546/10540596
qsf lcd_v.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/352155/10577348
qmsg dianhuajifei.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/422113/10663111
v image_ram.v
//
// Verilog Module dwt_final_lib.image_ram.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 10:08:02 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b
www.eeworm.com/read/422113/10663134
v final_ram.v
//
// Verilog Module dwt_final_lib.final_ram.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 14:19:42 05/10/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b