eeprom.map.qmsg

来自「eeprom的Verilog HDL源代码」· QMSG 代码 · 共 12 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 04 10:07:59 2007 " "Info: Processing started: Sun Nov 04 10:07:59 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off eeprom -c eeprom --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off eeprom -c eeprom --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "eeprom.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file eeprom.v" { { "Info" "ISGN_ENTITY_NAME" "1 eeprom " "Info: Found entity 1: eeprom" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "eeprom " "Info: Elaborating entity \"eeprom\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "eeprom.v(324) " "Warning: (10270) Verilog HDL statement warning at eeprom.v(324): incomplete Case Statement has no default case item" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 324 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "eeprom.v(324) " "Info: Verilog HDL Case Statement information at eeprom.v(324): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 324 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "eeprom.v(324) " "Info: Verilog HDL Case Statement information at eeprom.v(324): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 324 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "eeprom.v(199) " "Info: Verilog HDL Case Statement information at eeprom.v(199): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 199 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "eeprom.v(82) " "Info: Verilog HDL Case Statement information at eeprom.v(82): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 82 0 0 } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 04 10:08:00 2007 " "Info: Processing ended: Sun Nov 04 10:08:00 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}