image_ram.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.image_ram.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 10:08:02 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module image_ram(clk,reset,in,out,addr,r_w_en,enable);
  
  //store the image in image ram as 8*8 blocks
  
  input clk,reset;
  input [7:0] in;
  input [12:0] addr;
  input r_w_en;
  input enable;
  
  output [7:0] out;
  
  reg [7:0] out;
  
  reg [7:0] mem [8191:0];
    
  always@(posedge clk or negedge reset)
  begin
    if(!reset)
    begin
      out<=8'b0;
    end
    else
    begin
      if(enable)
      begin        
      if(r_w_en==1'b0)    //read at active low
      out<=mem[addr];
       else
      mem[addr]<=in;
     end
    end
  end
   // ### Please start your Verilog code here ###
endmodule