dianhuajifei.map.qmsg

Verilog语言编写的电话计费系统

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 30 11:49:33 2008 " "Info: Processing started: Sat Aug 30 11:49:33 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianhuajifei -c dianhuajifei " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianhuajifei -c dianhuajifei" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianhuajifei.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dianhuajifei.v" { { "Info" "ISGN_ENTITY_NAME" "1 dianhuajifei " "Info: Found entity 1: dianhuajifei" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dianhuajifei " "Info: Elaborating entity \"dianhuajifei\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 dianhuajifei.v(23) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(23): truncated value with size 32 to match size of target (11)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 dianhuajifei.v(25) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(25): truncated value with size 32 to match size of target (1)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(48) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(48): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(50) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(50): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 dianhuajifei.v(52) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(52): truncated value with size 32 to match size of target (3)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(54) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(54): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 54 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 dianhuajifei.v(60) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(60): truncated value with size 32 to match size of target (1)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(61) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(61): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(65) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(65): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 dianhuajifei.v(75) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(75): truncated value with size 32 to match size of target (1)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(76) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(76): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(78) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(78): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(82) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(82): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 dianhuajifei.v(84) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(84): truncated value with size 32 to match size of target (3)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(85) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(85): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianhuajifei.v(87) " "Warning (10230): Verilog HDL assignment warning at dianhuajifei.v(87): truncated value with size 32 to match size of target (4)" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 87 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "set High " "Info: Power-up level of register \"set\" is not specified -- using power-up level of High to minimize register" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 21 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "set data_in VCC " "Warning: Reduced register \"set\" with stuck data_in port to stuck value VCC" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 21 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "reset_ena warn~reg0 " "Info: Duplicate register \"reset_ena\" merged to single register \"warn~reg0\"" {  } { { "dianhuajifei.v" "" { Text "D:/Program Files/altera/quartus60/win/dianhuajifei/dianhuajifei.v" 21 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "194 " "Info: Implemented 194 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "165 " "Info: Implemented 165 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 30 11:49:37 2008 " "Info: Processing ended: Sat Aug 30 11:49:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}