代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/154098/5642267
sprj module_b.sprj
`timescale 1ns/1ns
`include "../module_b.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/154098/5642277
prj module_b.prj
`timescale 1ns/1ns
`include "../module_b.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/154079/5642915
prj cnt_vlog.prj
`timescale 1ns/1ns
`include "cnt_vlog.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/154079/5642929
sprj cnt_vlog.sprj
`timescale 1ns/1ns
`include "cnt_vlog.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/154076/5643055
sprj top.sprj
`timescale 1ns/1ns
`include "dpram_core.v"
`include "top.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/154076/5643057
prj top.prj
`timescale 1ns/1ns
`include "dpram_core.v"
`include "top.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/198746/6786442
npl mvbc3.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT mvbc3
DESIGN mvbc3
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s300e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEV
www.eeworm.com/read/474148/6815658
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity tdelay is
generic(
L_t : integer := 16
);
end tdelay;
www.eeworm.com/read/395090/8196726
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity EEPROM is
generic(
r7 : integer := 175;
w7 : integer := 174;
r6 : integer := 173;
www.eeworm.com/read/294565/8218221
plg bulkloop.plg
礦ision3 Build Log
Project:
F:\公共磁盘\05级工作区\qigongbo\68013开发板\测试程序源代码（包括VC工程文件及Firmware,Verilog代码）\USB2.0+FPGA_EXAMPLES\SLAVE FIFO8测试\固件\bulkloop.uv2
Project