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The VHDL file dpram_rtl.vhd is reused from the SPDIF interface project. Fetch the file spdif_interface/rtl/vhdl/dpram_rtl.vhd.

sch2vhdl -family spartan2 -flat -suppress -w top.sch top.vhf sch2vhdl -family spartan2 -flat -suppress -w top.sch top.vhf sch2vhdl -family spartan2 -flat -suppress -w top.sch top.vhf sch2vhdl -fami

-- Xilinx Vhdl produced by program ngd2vhdl F.23 -- Command: -rpw 100 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log uc_interface.nga uc_interface_timesim.vhd -- Input file: uc_interface.nga

-- Xilinx Vhdl produced by program ngd2vhdl F.28 -- Command: -rpw 100 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log music.nga music_timesim.vhd -- Input file: music.nga -- Output file: music

-- Xilinx Vhdl produced by program ngd2vhdl F.30a -- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log debug_detect_peakvalue.nga debug_detect_peakvalue_timesim.vh

# VHDL : Create Schematic Symbol __projnav/tb.rsp djs.spl __projnav/vhd2spl.err # VHDL : Create Schematic Symbol __projnav/tb.rsp fpq1s.spl __projnav/vhd2spl.err # VHDL : Create Schematic Symb

-- Xilinx Vhdl produced by program ngd2vhdl F.23 -- Command: -rpw 100 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log uc_interface.nga uc_interface_timesim.vhd -- Input file: uc_interface.nga

-- Xilinx Vhdl produced by program ngd2vhdl F.23 -- Command: -rpw 100 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log uc_interface.nga uc_interface_timesim.vhd -- Input file: uc_interface.nga

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib