debug_detect_peakvalue_timesim.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

-- Xilinx Vhdl produced by program ngd2vhdl F.30a
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log debug_detect_peakvalue.nga debug_detect_peakvalue_timesim.vhd 
-- Input file: debug_detect_peakvalue.nga
-- Output file: debug_detect_peakvalue_timesim.vhd
-- Design name: Debug_Detect_Peakvalue
-- Xilinx: D:/Xilinx
-- # of Entities: 1
-- Device: 2v3000fg676-5 (PRODUCTION 1.114 2002-12-13, STEPPING 0)

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity Debug_Detect_Peakvalue is
  port (
    Enable_Detect : in STD_LOGIC := 'X'; 
    Detect : out STD_LOGIC; 
    SampleClk : in STD_LOGIC := 'X'; 
    Sum_Q_Prompt : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    CodeOfSlew : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
    Sum_I_Prompt : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end Debug_Detect_Peakvalue;

architecture Structure of Debug_Detect_Peakvalue is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal flagofdetect_1_cry_5_O : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O : STD_LOGIC; 
  signal flagofdetect_1_cry_29_O : STD_LOGIC; 
  signal flagofdetect_1_cry_31_O : STD_LOGIC; 
  signal un24_countofcompute_n : STD_LOGIC; 
  signal SampleClk_c : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal un7_resultoftemp_axb_0 : STD_LOGIC; 
  signal un7_resultoftemp_s_1_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_1_O : STD_LOGIC; 
  signal un7_resultoftemp_s_2_n : STD_LOGIC; 
  signal un7_resultoftemp_s_3_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_3_O : STD_LOGIC; 
  signal un7_resultoftemp_s_4_n : STD_LOGIC; 
  signal un7_resultoftemp_s_5_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_5_O : STD_LOGIC; 
  signal un7_resultoftemp_s_6_n : STD_LOGIC; 
  signal un7_resultoftemp_s_7_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_7_O : STD_LOGIC; 
  signal un7_resultoftemp_s_8_n : STD_LOGIC; 
  signal un7_resultoftemp_s_9_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_9_O : STD_LOGIC; 
  signal un7_resultoftemp_s_10_n : STD_LOGIC; 
  signal un7_resultoftemp_s_11_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_11_O : STD_LOGIC; 
  signal un7_resultoftemp_s_12_n : STD_LOGIC; 
  signal un7_resultoftemp_s_13_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_13_O : STD_LOGIC; 
  signal un7_resultoftemp_s_14_n : STD_LOGIC; 
  signal un7_resultoftemp_s_15_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_15_O : STD_LOGIC; 
  signal un7_resultoftemp_s_16_n : STD_LOGIC; 
  signal un7_resultoftemp_s_17_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_17_O : STD_LOGIC; 
  signal un7_resultoftemp_s_18_n : STD_LOGIC; 
  signal un7_resultoftemp_s_19_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_19_O : STD_LOGIC; 
  signal un7_resultoftemp_s_20_n : STD_LOGIC; 
  signal un7_resultoftemp_s_21_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_21_O : STD_LOGIC; 
  signal un7_resultoftemp_s_22_n : STD_LOGIC; 
  signal un7_resultoftemp_s_23_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_23_O : STD_LOGIC; 
  signal un7_resultoftemp_s_24_n : STD_LOGIC; 
  signal un7_resultoftemp_s_25_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_25_O : STD_LOGIC; 
  signal un7_resultoftemp_s_26_n : STD_LOGIC; 
  signal un7_resultoftemp_s_27_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_27_O : STD_LOGIC; 
  signal un7_resultoftemp_s_28_n : STD_LOGIC; 
  signal un7_resultoftemp_s_29_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_29_O : STD_LOGIC; 
  signal un7_resultoftemp_s_30_n : STD_LOGIC; 
  signal un7_resultoftemp_s_31_n : STD_LOGIC; 
  signal un7_resultoftemp_cry_31_O : STD_LOGIC; 
  signal un7_resultoftemp_axb_32 : STD_LOGIC; 
  signal un7_resultoftemp_s_32_n : STD_LOGIC; 
  signal Detect_c : STD_LOGIC; 
  signal un1_flagofcompute_1_n : STD_LOGIC; 
  signal un1_flagofcompute_2_i : STD_LOGIC; 
  signal Enable_Detect_c : STD_LOGIC; 
  signal SampleClk_ibuf_IBUFG : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal flagofcompute : STD_LOGIC; 
  signal un6_countofcompute_axbxc1_O : STD_LOGIC; 
  signal countofcompute_3_0_O : STD_LOGIC; 
  signal un7_flagofcompute_n : STD_LOGIC; 
  signal countofcompute_3_2_O : STD_LOGIC; 
  signal un27_countofcompute_i : STD_LOGIC; 
  signal flagofgetcodeslew : STD_LOGIC; 
  signal flagofdetect_1_cry_1_O : STD_LOGIC; 
  signal flagofdetect_1_cry_3_O : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_2 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_3 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_4 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_5 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_6 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_7 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_8 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_9 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_10 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_11 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_12 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal resultoftemp_7_rt : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_LOGIC_ZERO : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_7_O_CYSELF : STD_LOGIC; 
  signal resultoftemp_6_rt : STD_LOGIC; 
  signal resultoftemp_9_rt : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_LOGIC_ZERO : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_9_O_CYSELF : STD_LOGIC; 
  signal resultoftemp_8_rt : STD_LOGIC; 
  signal resultoftemp_10_CLKINV : STD_LOGIC; 
  signal un7_resultoftemp_axb_11 : STD_LOGIC; 
  signal resultoftemp_10_CYSELG : STD_LOGIC; 
  signal resultoftemp_10_CY0G : STD_LOGIC; 
  signal resultoftemp_10_CYMUXF2 : STD_LOGIC; 
  signal resultoftemp_10_CYMUXG2 : STD_LOGIC; 
  signal resultoftemp_10_FASTCARRY : STD_LOGIC; 
  signal resultoftemp_10_CYAND : STD_LOGIC; 
  signal resultoftemp_10_CYMUXFAST : STD_LOGIC; 
  signal resultoftemp_10_CYSELF : STD_LOGIC; 
  signal un7_resultoftemp_cry_10_O : STD_LOGIC; 
  signal resultoftemp_10_XORG : STD_LOGIC; 
  signal resultoftemp_10_DYMUX : STD_LOGIC; 
  signal un7_resultoftemp_axb_10 : STD_LOGIC; 
  signal resultoftemp_10_CY0F : STD_LOGIC; 
  signal resultoftemp_10_CYINIT : STD_LOGIC; 
  signal resultoftemp_10_XORF : STD_LOGIC; 
  signal resultoftemp_10_DXMUX : STD_LOGIC; 
  signal resultoftemp_12_CLKINV : STD_LOGIC; 
  signal un7_resultoftemp_axb_13 : STD_LOGIC; 
  signal resultoftemp_12_CYSELG : STD_LOGIC; 
  signal resultoftemp_12_CY0G : STD_LOGIC; 
  signal resultoftemp_12_CYMUXF2 : STD_LOGIC; 
  signal resultoftemp_12_CYMUXG2 : STD_LOGIC; 
  signal resultoftemp_12_FASTCARRY : STD_LOGIC; 
  signal resultoftemp_12_CYAND : STD_LOGIC; 
  signal resultoftemp_12_CYMUXFAST : STD_LOGIC; 
  signal resultoftemp_12_CYSELF : STD_LOGIC; 
  signal un7_resultoftemp_cry_12_O : STD_LOGIC; 
  signal resultoftemp_12_XORG : STD_LOGIC; 
  signal resultoftemp_12_DYMUX : STD_LOGIC; 
  signal un7_resultoftemp_axb_12 : STD_LOGIC; 
  signal resultoftemp_12_CY0F : STD_LOGIC; 
  signal resultoftemp_12_CYINIT : STD_LOGIC; 
  signal resultoftemp_12_XORF : STD_LOGIC; 
  signal resultoftemp_12_DXMUX : STD_LOGIC; 
  signal resultoftemp_14_CLKINV : STD_LOGIC; 
  signal un7_resultoftemp_axb_15 : STD_LOGIC; 
  signal resultoftemp_14_CYSELG : STD_LOGIC; 
  signal resultoftemp_14_CY0G : STD_LOGIC; 
  signal resultoftemp_14_CYMUXF2 : STD_LOGIC; 
  signal resultoftemp_14_CYMUXG2 : STD_LOGIC; 
  signal resultoftemp_14_FASTCARRY : STD_LOGIC; 
  signal resultoftemp_14_CYAND : STD_LOGIC; 
  signal resultoftemp_14_CYMUXFAST : STD_LOGIC; 
  signal resultoftemp_14_CYSELF : STD_LOGIC; 
  signal un7_resultoftemp_cry_14_O : STD_LOGIC; 
  signal resultoftemp_14_XORG : STD_LOGIC; 
  signal resultoftemp_14_DYMUX : STD_LOGIC; 
  signal un7_resultoftemp_axb_14 : STD_LOGIC; 
  signal resultoftemp_14_CY0F : STD_LOGIC; 
  signal resultoftemp_14_CYINIT : STD_LOGIC; 
  signal resultoftemp_14_XORF : STD_LOGIC; 
  signal resultoftemp_14_DXMUX : STD_LOGIC; 
  signal resultoftemp_16_CLKINV : STD_LOGIC; 
  signal un7_resultoftemp_axb_17 : STD_LOGIC; 
  signal resultoftemp_16_CYSELG : STD_LOGIC; 
  signal resultoftemp_16_CY0G : STD_LOGIC; 
  signal resultoftemp_16_CYMUXF2 : STD_LOGIC; 
  signal resultoftemp_16_CYMUXG2 : STD_LOGIC; 
  signal resultoftemp_16_FASTCARRY : STD_LOGIC; 
  signal resultoftemp_16_CYAND : STD_LOGIC; 
  signal resultoftemp_16_CYMUXFAST : STD_LOGIC; 
  signal resultoftemp_16_CYSELF : STD_LOGIC; 
  signal un7_resultoftemp_cry_16_O : STD_LOGIC; 
  signal resultoftemp_16_XORG : STD_LOGIC; 
  signal resultoftemp_16_DYMUX : STD_LOGIC; 
  signal un7_resultoftemp_axb_16 : STD_LOGIC; 
  signal resultoftemp_16_CY0F : STD_LOGIC; 
  signal resultoftemp_16_CYINIT : STD_LOGIC; 
  signal resultoftemp_16_XORF : STD_LOGIC; 
  signal resultoftemp_16_DXMUX : STD_LOGIC; 
  signal resultoftemp_11_rt : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_LOGIC_ZERO : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_11_O_CYSELF : STD_LOGIC; 
  signal resultoftemp_10_rt : STD_LOGIC; 
  signal resultoftemp_13_rt : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_LOGIC_ZERO : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_13_O_CYSELF : STD_LOGIC; 
  signal resultoftemp_12_rt : STD_LOGIC; 
  signal N_117_i : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_CYSELF : STD_LOGIC; 
  signal resultoftemp_14_rt : STD_LOGIC; 
  signal flagofdetect_1_cry_15_O_LOGIC_ZERO : STD_LOGIC; 
  signal N_119_i : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_17_O_CYSELF : STD_LOGIC; 
  signal N_118_i : STD_LOGIC; 
  signal N_121_i : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_19_O_CYSELF : STD_LOGIC; 
  signal N_120_i : STD_LOGIC; 
  signal N_123_i : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_21_O_CYSELF : STD_LOGIC; 
  signal N_122_i : STD_LOGIC; 
  signal N_125_i : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_23_O_CYSELF : STD_LOGIC; 
  signal N_124_i : STD_LOGIC; 
  signal N_127_i : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_25_O_CYSELF : STD_LOGIC; 
  signal N_126_i : STD_LOGIC; 
  signal N_129_i : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_CYAND : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_CYMUXFAST : STD_LOGIC; 
  signal flagofdetect_1_cry_27_O_CYSELF : STD_LOGIC; 
  signal N_128_i : STD_LOGIC; 
  signal N_131_i : STD_LOGIC; 
  signal flagofdetect_1_cry_29_O_CYSELG : STD_LOGIC; 
  signal flagofdetect_1_cry_29_O_LOGIC_ONE : STD_LOGIC; 
  signal flagofdetect_1_cry_29_O_CYMUXF2 : STD_LOGIC; 
  signal flagofdetect_1_cry_29_O_CYMUXG2 : STD_LOGIC; 
  signal flagofdetect_1_cry_29_O_FASTCARRY : STD_LOGIC; 
  signal flagofdetect_1_cry_29_O_CYAND : STD_LOGIC;