uc_interface_timesim.vhd

8051接口VHDL代码

-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -rpw 100 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log uc_interface.nga uc_interface_timesim.vhd 
-- Input file: uc_interface.nga
-- Output file: uc_interface_timesim.vhd
-- Design name: uc_interface
-- Xilinx: C:/Xilinx_WebPACK_51
-- # of Entities: 1
-- Device: XCR3064XL-6-VQ100

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity uc_interface is
  port (
    rd_n : in STD_LOGIC := 'X'; 
    wr_n : in STD_LOGIC := 'X'; 
    ale_n : in STD_LOGIC := 'X'; 
    psen_n : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    dataout_load : in STD_LOGIC := 'X'; 
    data_rdy : in STD_LOGIC := 'X'; 
    need_data : in STD_LOGIC := 'X'; 
    error : in STD_LOGIC := 'X'; 
    done : in STD_LOGIC := 'X'; 
    app_en : out STD_LOGIC; 
    data_rdy_reset : out STD_LOGIC; 
    error_reset : out STD_LOGIC; 
    int_n : out STD_LOGIC; 
    need_data_reset : out STD_LOGIC; 
    start : out STD_LOGIC; 
    addr : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    addr_data : inout STD_LOGIC_VECTOR ( 7 downto 0 ); 
    app_data : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    ctrl_bits : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
    data_in : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end uc_interface;

architecture Structure of uc_interface is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal addr_data_0_MC_Q : STD_LOGIC; 
  signal addr_data_0_MC_OE : STD_LOGIC; 
  signal addr_data_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal FOOBAR3_ctinst_7 : STD_LOGIC; 
  signal addr_data_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_0_MC_D : STD_LOGIC; 
  signal clk_II_FCLK : STD_LOGIC; 
  signal reset_II_UIM : STD_LOGIC; 
  signal addr_data_0_MC_D1 : STD_LOGIC; 
  signal addr_data_0_MC_UIM : STD_LOGIC; 
  signal N_PZ_236 : STD_LOGIC; 
  signal addr_data_0_MC_D2_PT_0 : STD_LOGIC; 
  signal rd_n_II_UIM : STD_LOGIC; 
  signal prs_state_fft1 : STD_LOGIC; 
  signal prs_state_fft2 : STD_LOGIC; 
  signal dataout_en : STD_LOGIC; 
  signal addr_data_0_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_0_MC_UIM : STD_LOGIC; 
  signal datain_en : STD_LOGIC; 
  signal addr_data_0_MC_D2_PT_2 : STD_LOGIC; 
  signal ctrl_bits_0_MC_UIM : STD_LOGIC; 
  signal cntrl_en : STD_LOGIC; 
  signal stat_en : STD_LOGIC; 
  signal addr_data_0_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_0_MC_D2 : STD_LOGIC; 
  signal addr_data_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal FOOBAR1_ctinst_7 : STD_LOGIC; 
  signal prs_state_fft1_MC_Q : STD_LOGIC; 
  signal prs_state_fft1_MC_R_OR_PRLD : STD_LOGIC; 
  signal prs_state_fft1_MC_D : STD_LOGIC; 
  signal prs_state_fft1_MC_D1 : STD_LOGIC; 
  signal addr_match : STD_LOGIC; 
  signal prs_state_fft1_MC_D2_PT_0 : STD_LOGIC; 
  signal wr_n_II_UIM : STD_LOGIC; 
  signal prs_state_fft1_MC_D2_PT_1 : STD_LOGIC; 
  signal ale_n_II_UIM : STD_LOGIC; 
  signal psen_n_II_UIM : STD_LOGIC; 
  signal prs_state_fft1_MC_D2_PT_2 : STD_LOGIC; 
  signal prs_state_fft1_MC_D2 : STD_LOGIC; 
  signal prs_state_fft1_MC_D_TFF : STD_LOGIC; 
  signal prs_state_fft2_MC_Q : STD_LOGIC; 
  signal prs_state_fft2_MC_R_OR_PRLD : STD_LOGIC; 
  signal prs_state_fft2_MC_D : STD_LOGIC; 
  signal prs_state_fft2_MC_D1 : STD_LOGIC; 
  signal prs_state_fft2_MC_D2_PT_0 : STD_LOGIC; 
  signal prs_state_fft2_MC_D2_PT_1 : STD_LOGIC; 
  signal prs_state_fft2_MC_D2_PT_2 : STD_LOGIC; 
  signal prs_state_fft2_MC_D2 : STD_LOGIC; 
  signal prs_state_fft2_MC_D_TFF : STD_LOGIC; 
  signal ale_n_II_FCLK : STD_LOGIC; 
  signal addr_match_MC_Q : STD_LOGIC; 
  signal addr_match_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_match_MC_D : STD_LOGIC; 
  signal addr_0_II_UIM : STD_LOGIC; 
  signal addr_1_II_UIM : STD_LOGIC; 
  signal addr_2_II_UIM : STD_LOGIC; 
  signal addr_3_II_UIM : STD_LOGIC; 
  signal addr_4_II_UIM : STD_LOGIC; 
  signal addr_5_II_UIM : STD_LOGIC; 
  signal addr_6_II_UIM : STD_LOGIC; 
  signal addr_7_II_UIM : STD_LOGIC; 
  signal addr_match_MC_D1_PT_0 : STD_LOGIC; 
  signal addr_match_MC_D1 : STD_LOGIC; 
  signal addr_match_MC_D2 : STD_LOGIC; 
  signal N_PZ_236_MC_Q : STD_LOGIC; 
  signal N_PZ_236_MC_D : STD_LOGIC; 
  signal N_PZ_236_MC_D1 : STD_LOGIC; 
  signal N_PZ_236_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_236_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_236_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_236_MC_D2_PT_3 : STD_LOGIC; 
  signal N_PZ_236_MC_D2 : STD_LOGIC; 
  signal dataout_en_MC_Q : STD_LOGIC; 
  signal dataout_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal dataout_en_MC_D : STD_LOGIC; 
  signal dataout_en_MC_D1_PT_0 : STD_LOGIC; 
  signal dataout_en_MC_D1 : STD_LOGIC; 
  signal dataout_en_MC_D2 : STD_LOGIC; 
  signal address_low_0_MC_Q : STD_LOGIC; 
  signal address_low_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_0_MC_D : STD_LOGIC; 
  signal ale_n_II_FCLK_tsimcreated_inv_Q : STD_LOGIC; 
  signal addr_data_0_II_UIM : STD_LOGIC; 
  signal address_low_0_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_0_MC_D1 : STD_LOGIC; 
  signal address_low_0_MC_D2 : STD_LOGIC; 
  signal address_low_1_MC_Q : STD_LOGIC; 
  signal address_low_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_1_MC_D : STD_LOGIC; 
  signal addr_data_1_II_UIM : STD_LOGIC; 
  signal address_low_1_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_1_MC_D1 : STD_LOGIC; 
  signal address_low_1_MC_D2 : STD_LOGIC; 
  signal address_low_2_MC_Q : STD_LOGIC; 
  signal address_low_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_2_MC_D : STD_LOGIC; 
  signal addr_data_2_II_UIM : STD_LOGIC; 
  signal address_low_2_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_2_MC_D1 : STD_LOGIC; 
  signal address_low_2_MC_D2 : STD_LOGIC; 
  signal address_low_3_MC_Q : STD_LOGIC; 
  signal address_low_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_3_MC_D : STD_LOGIC; 
  signal addr_data_3_II_UIM : STD_LOGIC; 
  signal address_low_3_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_3_MC_D1 : STD_LOGIC; 
  signal address_low_3_MC_D2 : STD_LOGIC; 
  signal address_low_4_MC_Q : STD_LOGIC; 
  signal address_low_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_4_MC_D : STD_LOGIC; 
  signal addr_data_4_II_UIM : STD_LOGIC; 
  signal address_low_4_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_4_MC_D1 : STD_LOGIC; 
  signal address_low_4_MC_D2 : STD_LOGIC; 
  signal address_low_5_MC_Q : STD_LOGIC; 
  signal address_low_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_5_MC_D : STD_LOGIC; 
  signal addr_data_5_II_UIM : STD_LOGIC; 
  signal address_low_5_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_5_MC_D1 : STD_LOGIC; 
  signal address_low_5_MC_D2 : STD_LOGIC; 
  signal address_low_6_MC_Q : STD_LOGIC; 
  signal address_low_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_6_MC_D : STD_LOGIC; 
  signal addr_data_6_II_UIM : STD_LOGIC; 
  signal address_low_6_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_6_MC_D1 : STD_LOGIC; 
  signal address_low_6_MC_D2 : STD_LOGIC; 
  signal address_low_7_MC_Q : STD_LOGIC; 
  signal address_low_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal address_low_7_MC_D : STD_LOGIC; 
  signal addr_data_7_II_UIM : STD_LOGIC; 
  signal address_low_7_MC_D1_PT_0 : STD_LOGIC; 
  signal address_low_7_MC_D1 : STD_LOGIC; 
  signal address_low_7_MC_D2 : STD_LOGIC; 
  signal datain_en_MC_Q : STD_LOGIC; 
  signal datain_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal datain_en_MC_D : STD_LOGIC; 
  signal datain_en_MC_D1_PT_0 : STD_LOGIC; 
  signal datain_en_MC_D1 : STD_LOGIC; 
  signal datain_en_MC_D2 : STD_LOGIC; 
  signal cntrl_en_MC_Q : STD_LOGIC; 
  signal cntrl_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal cntrl_en_MC_D : STD_LOGIC; 
  signal cntrl_en_MC_D1_PT_0 : STD_LOGIC; 
  signal cntrl_en_MC_D1 : STD_LOGIC; 
  signal cntrl_en_MC_D2 : STD_LOGIC; 
  signal stat_en_MC_Q : STD_LOGIC; 
  signal stat_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal stat_en_MC_D : STD_LOGIC; 
  signal stat_en_MC_D1_PT_0 : STD_LOGIC; 
  signal stat_en_MC_D1 : STD_LOGIC; 
  signal stat_en_MC_D2 : STD_LOGIC; 
  signal data_out_0_MC_Q : STD_LOGIC; 
  signal data_out_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_0_MC_D : STD_LOGIC; 
  signal data_out_0_MC_D1 : STD_LOGIC; 
  signal app_en_MC_UIM : STD_LOGIC; 
  signal dataout_load_II_UIM : STD_LOGIC; 
  signal data_out_0_MC_D2_PT_0 : STD_LOGIC; 
  signal app_data_0_II_UIM : STD_LOGIC; 
  signal data_out_0_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_0_MC_D2 : STD_LOGIC; 
  signal app_en_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal app_en_MC_Q : STD_LOGIC; 
  signal app_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal app_en_MC_D : STD_LOGIC; 
  signal app_en_MC_D1 : STD_LOGIC; 
  signal app_en_MC_D2_PT_0 : STD_LOGIC; 
  signal app_en_MC_D2_PT_1 : STD_LOGIC; 
  signal app_en_MC_D2 : STD_LOGIC; 
  signal app_en_MC_D_TFF : STD_LOGIC; 
  signal data_in_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_0_MC_Q : STD_LOGIC; 
  signal data_in_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_0_MC_D : STD_LOGIC; 
  signal data_in_0_MC_D1 : STD_LOGIC; 
  signal data_in_0_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_0_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_0_MC_D2 : STD_LOGIC; 
  signal data_in_0_MC_D_TFF : STD_LOGIC; 
  signal ctrl_bits_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ctrl_bits_0_MC_Q : STD_LOGIC; 
  signal ctrl_bits_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal ctrl_bits_0_MC_D : STD_LOGIC; 
  signal ctrl_bits_0_MC_D1 : STD_LOGIC; 
  signal ctrl_bits_0_MC_D2_PT_0 : STD_LOGIC; 
  signal ctrl_bits_0_MC_D2_PT_1 : STD_LOGIC; 
  signal ctrl_bits_0_MC_D2 : STD_LOGIC; 
  signal ctrl_bits_0_MC_D_TFF : STD_LOGIC; 
  signal addr_data_1_MC_Q : STD_LOGIC; 
  signal addr_data_1_MC_OE : STD_LOGIC; 
  signal addr_data_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_1_MC_D : STD_LOGIC; 
  signal addr_data_1_MC_D1 : STD_LOGIC; 
  signal addr_data_1_MC_UIM : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_1_MC_UIM : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_2 : STD_LOGIC; 
  signal ctrl_bits_1_MC_UIM : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_1_MC_D2 : STD_LOGIC; 
  signal addr_data_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal data_out_1_MC_Q : STD_LOGIC; 
  signal data_out_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_1_MC_D : STD_LOGIC; 
  signal data_out_1_MC_D1 : STD_LOGIC; 
  signal app_data_1_II_UIM : STD_LOGIC; 
  signal data_out_1_MC_D2_PT_0 : STD_LOGIC; 
  signal data_out_1_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_1_MC_D2 : STD_LOGIC; 
  signal data_in_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_1_MC_Q : STD_LOGIC; 
  signal data_in_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_1_MC_D : STD_LOGIC; 
  signal data_in_1_MC_D1 : STD_LOGIC; 
  signal data_in_1_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_1_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_1_MC_D2 : STD_LOGIC; 
  signal data_in_1_MC_D_TFF : STD_LOGIC; 
  signal ctrl_bits_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ctrl_bits_1_MC_Q : STD_LOGIC; 
  signal ctrl_bits_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal ctrl_bits_1_MC_D : STD_LOGIC; 
  signal ctrl_bits_1_MC_D1 : STD_LOGIC; 
  signal ctrl_bits_1_MC_D2_PT_0 : STD_LOGIC; 
  signal ctrl_bits_1_MC_D2_PT_1 : STD_LOGIC; 
  signal ctrl_bits_1_MC_D2 : STD_LOGIC; 
  signal ctrl_bits_1_MC_D_TFF : STD_LOGIC; 
  signal addr_data_2_MC_Q : STD_LOGIC; 
  signal addr_data_2_MC_OE : STD_LOGIC; 
  signal addr_data_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_2_MC_D : STD_LOGIC; 
  signal addr_data_2_MC_D1 : STD_LOGIC; 
  signal addr_data_2_MC_UIM : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_2_MC_UIM : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_2 : STD_LOGIC; 
  signal ctrl_bits_2_MC_UIM : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_2_MC_D2 : STD_LOGIC; 
  signal addr_data_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal data_out_2_MC_Q : STD_LOGIC; 
  signal data_out_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_2_MC_D : STD_LOGIC; 
  signal data_out_2_MC_D1 : STD_LOGIC; 
  signal app_data_2_II_UIM : STD_LOGIC; 
  signal data_out_2_MC_D2_PT_0 : STD_LOGIC; 
  signal data_out_2_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_2_MC_D2 : STD_LOGIC; 
  signal data_in_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_2_MC_Q : STD_LOGIC; 
  signal data_in_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_2_MC_D : STD_LOGIC; 
  signal data_in_2_MC_D1 : STD_LOGIC; 
  signal data_in_2_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_2_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_2_MC_D2 : STD_LOGIC; 
  signal data_in_2_MC_D_TFF : STD_LOGIC; 
  signal ctrl_bits_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ctrl_bits_2_MC_Q : STD_LOGIC; 
  signal ctrl_bits_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal ctrl_bits_2_MC_D : STD_LOGIC; 
  signal ctrl_bits_2_MC_D1 : STD_LOGIC; 
  signal ctrl_bits_2_MC_D2_PT_0 : STD_LOGIC; 
  signal ctrl_bits_2_MC_D2_PT_1 : STD_LOGIC; 
  signal ctrl_bits_2_MC_D2 : STD_LOGIC; 
  signal ctrl_bits_2_MC_D_TFF : STD_LOGIC; 
  signal addr_data_3_MC_Q : STD_LOGIC; 
  signal addr_data_3_MC_OE : STD_LOGIC; 
  signal addr_data_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_3_MC_R_OR_PRLD : STD_LOGIC;