music_timesim.vhd

用CPLD做音乐发生器

-- Xilinx Vhdl produced by program ngd2vhdl F.28
-- Command: -rpw 100 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log music.nga music_timesim.vhd 
-- Input file: music.nga
-- Output file: music_timesim.vhd
-- Design name: music
-- Xilinx: C:/Xilinx
-- # of Entities: 1
-- Device: XC95108-7-PC84

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity music is
  port (
    enable1 : in STD_LOGIC := 'X'; 
    enable2 : in STD_LOGIC := 'X'; 
    inclk : in STD_LOGIC := 'X'; 
    spk : out STD_LOGIC 
  );
end music;

architecture Structure of music is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal spk_obuf_Q : STD_LOGIC; 
  signal spk_obuf_Q_0 : STD_LOGIC; 
  signal spk_obuf_D : STD_LOGIC; 
  signal spk_obuf_CLKF : STD_LOGIC; 
  signal clk : STD_LOGIC; 
  signal spk_obuf_CLKF_PT_0 : STD_LOGIC; 
  signal spk_obuf_D1 : STD_LOGIC; 
  signal EXP16_EXP : STD_LOGIC; 
  signal spk_obuf_D2_PT_0 : STD_LOGIC; 
  signal tone_count_1_FBK : STD_LOGIC; 
  signal tone_count_2_FBK : STD_LOGIC; 
  signal tone_count_3_FBK : STD_LOGIC; 
  signal tone_count_4_FBK : STD_LOGIC; 
  signal tone_count_5_FBK : STD_LOGIC; 
  signal tone_count_6_FBK : STD_LOGIC; 
  signal tone_count_7_FBK : STD_LOGIC; 
  signal tone_count_8_FBK : STD_LOGIC; 
  signal tone_count_9_FBK : STD_LOGIC; 
  signal spk_obuf_FBK : STD_LOGIC; 
  signal spk_obuf_D2_PT_1 : STD_LOGIC; 
  signal spk_obuf_D2 : STD_LOGIC; 
  signal spk_obuf_D_TFF : STD_LOGIC; 
  signal spk_obuf_EXP_PT_0 : STD_LOGIC; 
  signal spk_obuf_EXP_PT_1 : STD_LOGIC; 
  signal spk_obuf_EXP_PT_2 : STD_LOGIC; 
  signal spk_obuf_EXP : STD_LOGIC; 
  signal EXP16_EXP_PT_0 : STD_LOGIC; 
  signal EXP16_EXP_PT_1 : STD_LOGIC; 
  signal EXP16_EXP_PT_2 : STD_LOGIC; 
  signal EXP16_EXP_PT_3 : STD_LOGIC; 
  signal EXP16_EXP_PT_4 : STD_LOGIC; 
  signal tone_count_1_Q : STD_LOGIC; 
  signal tone_count_1_D : STD_LOGIC; 
  signal tone_count_1_CLKF : STD_LOGIC; 
  signal tone_count_1_CLKF_PT_0 : STD_LOGIC; 
  signal tone_count_1_D1 : STD_LOGIC; 
  signal tone_count_1_D2_PT_0 : STD_LOGIC; 
  signal tone_count_1_D2_PT_1 : STD_LOGIC; 
  signal tone_count_1_D2_PT_2 : STD_LOGIC; 
  signal tone_count_1_D2_PT_3 : STD_LOGIC; 
  signal tone_count_1_D2 : STD_LOGIC; 
  signal tone_count_1_D_TFF : STD_LOGIC; 
  signal tone_count_0_Q : STD_LOGIC; 
  signal tone_count_0_D : STD_LOGIC; 
  signal tone_count_0_CLKF : STD_LOGIC; 
  signal clk_FBK : STD_LOGIC; 
  signal tone_count_0_CLKF_PT_0 : STD_LOGIC; 
  signal tone_count_0_D1 : STD_LOGIC; 
  signal tone_count_10_FBK : STD_LOGIC; 
  signal tone_count_0_FBK : STD_LOGIC; 
  signal tone_count_0_D2_PT_0 : STD_LOGIC; 
  signal tone_count_0_D2_PT_1 : STD_LOGIC; 
  signal tone_count_0_D2_PT_2 : STD_LOGIC; 
  signal tone_count_0_D2 : STD_LOGIC; 
  signal tone_count_0_D_TFF : STD_LOGIC; 
  signal tone_index_3_Q : STD_LOGIC; 
  signal tone_index_3_D : STD_LOGIC; 
  signal tone_index_3_CLKF : STD_LOGIC; 
  signal clk10 : STD_LOGIC; 
  signal tone_index_3_CLKF_PT_0 : STD_LOGIC; 
  signal tone_index_3_D1 : STD_LOGIC; 
  signal EXP3_EXP : STD_LOGIC; 
  signal tone_index_3_D2_PT_0 : STD_LOGIC; 
  signal EXP4_EXP : STD_LOGIC; 
  signal tone_index_3_D2_PT_1 : STD_LOGIC; 
  signal enable1_ibuf : STD_LOGIC; 
  signal enable2_ibuf : STD_LOGIC; 
  signal tone_index_3_D2_PT_2 : STD_LOGIC; 
  signal tone_index_3_D2_PT_3 : STD_LOGIC; 
  signal tone_index_3_D2_PT_4 : STD_LOGIC; 
  signal tone_index_3_D2_PT_5 : STD_LOGIC; 
  signal tone_index_3_D2 : STD_LOGIC; 
  signal EXP2_EXP : STD_LOGIC; 
  signal EXP3_EXP_PT_0 : STD_LOGIC; 
  signal EXP3_EXP_PT_1 : STD_LOGIC; 
  signal EXP3_EXP_PT_2 : STD_LOGIC; 
  signal EXP3_EXP_PT_3 : STD_LOGIC; 
  signal EXP3_EXP_PT_4 : STD_LOGIC; 
  signal EXP3_EXP_PT_5 : STD_LOGIC; 
  signal EXP1_EXP : STD_LOGIC; 
  signal EXP2_EXP_PT_0 : STD_LOGIC; 
  signal EXP2_EXP_PT_1 : STD_LOGIC; 
  signal EXP2_EXP_PT_2 : STD_LOGIC; 
  signal EXP2_EXP_PT_3 : STD_LOGIC; 
  signal EXP2_EXP_PT_4 : STD_LOGIC; 
  signal time2_0_FBK : STD_LOGIC; 
  signal EXP2_EXP_PT_5 : STD_LOGIC; 
  signal EXP1_EXP_PT_0 : STD_LOGIC; 
  signal time2_2_Q : STD_LOGIC; 
  signal time2_2_D : STD_LOGIC; 
  signal time2_2_CLKF : STD_LOGIC; 
  signal time2_2_SETF : STD_LOGIC; 
  signal time2_2_CLKF_PT_0 : STD_LOGIC; 
  signal time2_7_time2_7_SETF_INT_UIM : STD_LOGIC; 
  signal time2_2_SETF_PT_0 : STD_LOGIC; 
  signal time2_2_D1 : STD_LOGIC; 
  signal time2_4_EXP : STD_LOGIC; 
  signal time2_2_D2_PT_0 : STD_LOGIC; 
  signal time2_1_FBK : STD_LOGIC; 
  signal time2_2_D2_PT_1 : STD_LOGIC; 
  signal time2_2_D2_PT_2 : STD_LOGIC; 
  signal time2_2_D2 : STD_LOGIC; 
  signal time2_2_D_TFF : STD_LOGIC; 
  signal time2_2_FBK : STD_LOGIC; 
  signal time2_4_FBK : STD_LOGIC; 
  signal time2_5_FBK : STD_LOGIC; 
  signal time2_6_FBK : STD_LOGIC; 
  signal time2_7_FBK : STD_LOGIC; 
  signal time2_2_EXP_PT_0 : STD_LOGIC; 
  signal time2_2_EXP : STD_LOGIC; 
  signal time2_4_Q : STD_LOGIC; 
  signal time2_4_D : STD_LOGIC; 
  signal time2_4_CLKF : STD_LOGIC; 
  signal time2_4_SETF : STD_LOGIC; 
  signal time2_4_CLKF_PT_0 : STD_LOGIC; 
  signal time2_4_SETF_PT_0 : STD_LOGIC; 
  signal time2_4_D1 : STD_LOGIC; 
  signal time2_6_EXP : STD_LOGIC; 
  signal time2_4_D2_PT_0 : STD_LOGIC; 
  signal time2_4_D2_PT_1 : STD_LOGIC; 
  signal time2_4_D2 : STD_LOGIC; 
  signal time2_4_D_TFF : STD_LOGIC; 
  signal time2_4_EXP_PT_0 : STD_LOGIC; 
  signal time2_4_EXP_PT_1 : STD_LOGIC; 
  signal time2_6_Q : STD_LOGIC; 
  signal time2_6_RSTF : STD_LOGIC; 
  signal time2_6_R_OR_PRLD : STD_LOGIC; 
  signal time2_6_D : STD_LOGIC; 
  signal time2_6_CLKF : STD_LOGIC; 
  signal time2_6_CLKF_PT_0 : STD_LOGIC; 
  signal time2_6_RSTF_PT_0 : STD_LOGIC; 
  signal time2_6_D1 : STD_LOGIC; 
  signal time1_1_EXP : STD_LOGIC; 
  signal time2_6_D2_PT_0 : STD_LOGIC; 
  signal time2_6_D2 : STD_LOGIC; 
  signal time2_6_D_TFF : STD_LOGIC; 
  signal time2_6_EXP_PT_0 : STD_LOGIC; 
  signal time2_6_EXP_PT_1 : STD_LOGIC; 
  signal time2_6_EXP_PT_2 : STD_LOGIC; 
  signal time1_1_Q : STD_LOGIC; 
  signal time1_1_D : STD_LOGIC; 
  signal time1_1_CLKF : STD_LOGIC; 
  signal time1_1_SETF : STD_LOGIC; 
  signal time1_1_CLKF_PT_0 : STD_LOGIC; 
  signal time1_7_time1_7_SETF_INT_UIM : STD_LOGIC; 
  signal time1_1_SETF_PT_0 : STD_LOGIC; 
  signal time1_1_D1 : STD_LOGIC; 
  signal time1_1_D2_PT_0 : STD_LOGIC; 
  signal time1_2_EXP : STD_LOGIC; 
  signal time1_1_D2_PT_1 : STD_LOGIC; 
  signal time1_1_D2 : STD_LOGIC; 
  signal time1_1_D_TFF : STD_LOGIC; 
  signal time1_1_EXP_PT_0 : STD_LOGIC; 
  signal time1_1_EXP_PT_1 : STD_LOGIC; 
  signal time1_1_FBK : STD_LOGIC; 
  signal time1_0_Q : STD_LOGIC; 
  signal time1_0_RSTF : STD_LOGIC; 
  signal time1_0_R_OR_PRLD : STD_LOGIC; 
  signal time1_0_D : STD_LOGIC; 
  signal time1_0_CLKF : STD_LOGIC; 
  signal time1_0_CLKF_PT_0 : STD_LOGIC; 
  signal time1_0_RSTF_PT_0 : STD_LOGIC; 
  signal time1_0_D1 : STD_LOGIC; 
  signal time1_0_FBK : STD_LOGIC; 
  signal time1_3_FBK : STD_LOGIC; 
  signal time1_5_FBK : STD_LOGIC; 
  signal time1_6_FBK : STD_LOGIC; 
  signal time1_7_FBK : STD_LOGIC; 
  signal time1_0_D2_PT_0 : STD_LOGIC; 
  signal time1_0_D2 : STD_LOGIC; 
  signal time1_0_D_TFF : STD_LOGIC; 
  signal time1_2_Q : STD_LOGIC; 
  signal time1_2_D : STD_LOGIC; 
  signal time1_2_CLKF : STD_LOGIC; 
  signal time1_2_SETF : STD_LOGIC; 
  signal time1_2_CLKF_PT_0 : STD_LOGIC; 
  signal time1_2_SETF_PT_0 : STD_LOGIC; 
  signal time1_2_D1 : STD_LOGIC; 
  signal time1_2_D2_PT_0 : STD_LOGIC; 
  signal time1_2_FBK : STD_LOGIC; 
  signal time1_4_FBK : STD_LOGIC; 
  signal time1_2_D2_PT_1 : STD_LOGIC; 
  signal time1_2_D2 : STD_LOGIC; 
  signal time1_2_D_TFF : STD_LOGIC; 
  signal time1_2_EXP_PT_0 : STD_LOGIC; 
  signal time1_5_Q : STD_LOGIC; 
  signal time1_5_RSTF : STD_LOGIC; 
  signal time1_5_R_OR_PRLD : STD_LOGIC; 
  signal time1_5_D : STD_LOGIC; 
  signal time1_5_CLKF : STD_LOGIC; 
  signal time1_5_CLKF_PT_0 : STD_LOGIC; 
  signal time1_5_RSTF_PT_0 : STD_LOGIC; 
  signal time1_5_D1 : STD_LOGIC; 
  signal time1_5_D2_PT_0 : STD_LOGIC; 
  signal time1_5_D2 : STD_LOGIC; 
  signal time1_5_D_TFF : STD_LOGIC; 
  signal time1_4_Q : STD_LOGIC; 
  signal time1_4_D : STD_LOGIC; 
  signal time1_4_CLKF : STD_LOGIC; 
  signal time1_4_SETF : STD_LOGIC; 
  signal time1_4_CLKF_PT_0 : STD_LOGIC; 
  signal time1_4_SETF_PT_0 : STD_LOGIC; 
  signal time1_4_D1 : STD_LOGIC; 
  signal time1_4_D2_PT_0 : STD_LOGIC; 
  signal time1_4_D2_PT_1 : STD_LOGIC; 
  signal time1_4_D2 : STD_LOGIC; 
  signal time1_4_D_TFF : STD_LOGIC; 
  signal time1_3_Q : STD_LOGIC; 
  signal time1_3_RSTF : STD_LOGIC; 
  signal time1_3_R_OR_PRLD : STD_LOGIC; 
  signal time1_3_D : STD_LOGIC; 
  signal time1_3_CLKF : STD_LOGIC; 
  signal time1_3_CLKF_PT_0 : STD_LOGIC; 
  signal time1_3_RSTF_PT_0 : STD_LOGIC; 
  signal time1_3_D1 : STD_LOGIC; 
  signal time1_3_D2_PT_0 : STD_LOGIC; 
  signal time1_3_D2 : STD_LOGIC; 
  signal time1_3_D_TFF : STD_LOGIC; 
  signal clk10_Q : STD_LOGIC; 
  signal clk10_D : STD_LOGIC; 
  signal clk10_CLKF : STD_LOGIC;