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VHDL 的代码
ext_ram_lane1_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
ext_ram_lane3_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
mul_cpu_black_box_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
en
sys_ram_lane1_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
boot_monitor_rom_lane0_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
sys_ram_lane3_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
sys_ram_lane0_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
fpga_dsp_portlink.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
tag_mem.rvp
STYFILENAME=tag_mem.sty
PROJECT=tag_mem
ENTRY=Mixed Verilog/VHDL
WORKING_PATH=e:/3/tag_mem
MODULE=tag_mem_tst
TOP_FILE=tag_mem_tst.vhd
EDF_FILE_LIST=tag_mem.h tag_mem.vhd tag_mem0.vhd pll0.vhd t
vending.txt
entity DRINK_COUNT_VHDL is
port(NICKEL_IN, DIME_IN, QUARTER_IN, RESET: BOOLEAN;
CLK: BIT;
NICKEL_OUT, DIME_OUT, DISPENSE: out BOOLEAN);
end DRINK_COUNT_VHDL;
architecture BEHAVIOR of DRINK_COUNT_