mul_cpu_black_box_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity MUL_cpu_black_box_module is 
        port (
              -- inputs:
                 signal aclr : IN STD_LOGIC;
                 signal clken : IN STD_LOGIC;
                 signal clock : IN STD_LOGIC;
                 signal dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

end entity MUL_cpu_black_box_module;


architecture europa of MUL_cpu_black_box_module is
  component lpm_mult is
GENERIC (
      lpm_widths : NATURAL;
        lpm_representation : STRING;
        lpm_pipeline : NATURAL;
        lpm_widthp : NATURAL;
        lpm_widtha : NATURAL;
        lpm_widthb : NATURAL
      );
    PORT (
    signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        signal clken : IN STD_LOGIC;
        signal aclr : IN STD_LOGIC;
        signal clock : IN STD_LOGIC;
        signal dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
        signal datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
      );
  end component lpm_mult;
              signal internal_result1 :  STD_LOGIC_VECTOR (31 DOWNTO 0);
              signal p1_result :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  the_lpm_mult : lpm_mult
    generic map(
      lpm_widths => 32,
      lpm_representation => "UNSIGNED",
      lpm_pipeline => 2,
      lpm_widthp => 32,
      lpm_widtha => 16,
      lpm_widthb => 16
    )
    port map(
            clken => clken,
            result => internal_result1,
            aclr => aclr,
            clock => clock,
            dataa => dataa,
            datab => datab
    );

  --vhdl renameroo for output signals
  result <= internal_result1;
end europa;