fpga_dsp_portlink.qsf

implemention of FPGA and DSP linking port, using Asynchronous mode

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# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
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# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# The default values for assignments are stored in the file
#		FPGA_DSP_PortLink_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C7
set_global_assignment -name TOP_LEVEL_ENTITY FPGA_DSP_PortLink_BiBus_oneFIFO
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:03:18  DECEMBER 19, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name VECTOR_INPUT_SOURCE "E:\\ADFM\\FPGA_DSP_PortLink\\FPGA_DSP_PortLink_BiBus_oneFIFO.vwf"
set_location_assignment PIN_118 -to WE
set_location_assignment PIN_116 -to RE
set_location_assignment PIN_115 -to CS
set_global_assignment -name VHDL_FILE lpm_bustri1.vhd
set_global_assignment -name BDF_FILE FPGA_DSP_PortLink_BiBus.bdf
set_global_assignment -name VHDL_FILE COUT.vhd
set_global_assignment -name VHDL_FILE FIFO_WRN_ByDSP.vhd
set_global_assignment -name VHDL_FILE Freq_Divider_4.vhd
set_global_assignment -name VHDL_FILE FIFO_RDN_ByDSP.vhd
set_global_assignment -name BDF_FILE FPGA_DSP_PortLink.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE FPGA_DSP_PortLink.vwf
set_global_assignment -name BDF_FILE FPGA_DSP_PortLink_Inner.bdf
set_global_assignment -name VHDL_FILE MUX.vhd
set_global_assignment -name BDF_FILE fifo_test.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE fifo_test.vwf
set_global_assignment -name VHDL_FILE en_blk.vhd
set_global_assignment -name BDF_FILE BiPort_Test.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE BiPort_Test.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE FPGA_DSP_PortLink_BiBus.vwf
set_location_assignment PIN_144 -to Addr[0]
set_location_assignment PIN_143 -to Addr[1]
set_location_assignment PIN_113 -to TO_DSP[0]
set_location_assignment PIN_112 -to TO_DSP[1]
set_location_assignment PIN_110 -to TO_DSP[2]
set_location_assignment PIN_106 -to TO_DSP[3]
set_location_assignment PIN_105 -to TO_DSP[4]
set_location_assignment PIN_104 -to TO_DSP[5]
set_location_assignment PIN_103 -to TO_DSP[6]
set_location_assignment PIN_102 -to TO_DSP[7]
set_location_assignment PIN_101 -to TO_DSP[8]
set_location_assignment PIN_99 -to TO_DSP[9]
set_location_assignment PIN_97 -to TO_DSP[10]
set_location_assignment PIN_96 -to TO_DSP[11]
set_location_assignment PIN_95 -to TO_DSP[12]
set_location_assignment PIN_94 -to TO_DSP[13]
set_location_assignment PIN_92 -to TO_DSP[14]
set_location_assignment PIN_90 -to TO_DSP[15]
set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVCMOS
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name BDF_FILE FPGA_DSP_PortLink_BiBus_oneFIFO.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE FPGA_DSP_PortLink_BiBus_oneFIFO.vwf