boot_monitor_rom_lane0_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

library std;
use std.textio.all;

entity boot_monitor_rom_lane0_module is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

end entity boot_monitor_rom_lane0_module;


architecture europa of boot_monitor_rom_lane0_module is
  component lpm_rom is
GENERIC (
      lpm_address_control : STRING;
        lpm_width : NATURAL;
        suppress_memory_conversion_warnings : STRING;
        lpm_file : STRING;
        lpm_outdata : STRING;
        lpm_widthad : NATURAL
      );
    PORT (
    signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        signal address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        signal inclock : IN STD_LOGIC
      );
  end component lpm_rom;
              signal internal_q :  STD_LOGIC_VECTOR (31 DOWNTO 0);
              TYPE mem_array is ARRAY( 255 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
              signal rdclock :  STD_LOGIC;
              signal read_address :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal sim_delayed_address :  STD_LOGIC_VECTOR (7 DOWNTO 0);

begin

  read_address <= address;
  lpm_rom_component : lpm_rom
    generic map(
      lpm_address_control => "REGISTERED",
      lpm_width => 32,
      suppress_memory_conversion_warnings => "ON",
      lpm_file => "boot_monitor_rom_lane0.mif",
      lpm_outdata => "UNREGISTERED",
      lpm_widthad => 8
    )
    port map(
            address => read_address,
            q => internal_q,
            inclock => clk
    );

  rdclock <= clk;
  --vhdl renameroo for output signals
  q <= internal_q;
end europa;