代码搜索结果
找到约 10,000 项符合
VHDL 的代码
readme.txt
Please note:
Each example of VHDL code in "Fundamentals of Digital Logic with VHDL Design"
is contained in a sub-folder of the VHDLcode folder (examples that involve
schematics are also included)
sheet1.vhd
------------------------------------------------------------
-- VHDL Sheet1
-- 2010 5 27 17 30 38
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
------
sheet1.vhd
------------------------------------------------------------
-- VHDL Sheet1
-- 2010 5 27 16 52 21
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
------
bcd8.vhd
------------------------------------------------------------
-- VHDL BCD8
-- 2010 5 8 11 25 23
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
---------
sheet1.vhd
------------------------------------------------------------
-- VHDL Sheet1
-- 2010 5 27 17 30 38
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
------
sheet1.vhd
------------------------------------------------------------
-- VHDL Sheet1
-- 2010 5 27 16 52 21
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
------
bcd8.vhd
------------------------------------------------------------
-- VHDL BCD8
-- 2010 5 8 11 25 23
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
---------
readme.txt
Please note:
Each example of VHDL code in "Fundamentals of Digital Logic with VHDL Design"
is contained in a sub-folder of the VHDLcode folder (examples that involve
schematics are also included)
dianzheng.gfl
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
chw.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
cnta.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbo
modelsim.ini
[Library]
others = $MODEL_TECH/../modelsim.ini
fusion = $MODEL_TECH/../actel/vlog/fusion
syncad_vhdl_lib = C:\Actel\Libero8.0\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
[vsim]
I