bcd8.vhd

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-- VHDL BCD8
-- 2010 5 8 11 25 23
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL BCD8
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Library IEEE;
Use     IEEE.std_logic_1164.all;

  -- rtl_synthesis off
  Library BCD_LIB;
  Use BCD_LIB.all ;
  -- rtl_synthesis on

Entity BCD8 Is
  port
  (
    CLEAR  : In    STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=CLEAR
    CLOCK  : In    STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=CLOCK
    ENABLE : In    STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=ENABLE
    LOWER  : Out   STD_LOGIC_VECTOR(3 DOWNTO 0);             -- ObjectKind=Port|PrimaryId=LOWER[3..0]
    PARITY : Out   STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=PARITY
    UPPER  : Out   STD_LOGIC_VECTOR(3 DOWNTO 0);             -- ObjectKind=Port|PrimaryId=UPPER[3..0]
    URCO   : Out   STD_LOGIC                                 -- ObjectKind=Port|PrimaryId=URCO
  );
  attribute MacroCell : boolean;

End BCD8;
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architecture structure of BCD8 is
   Component BCD                                             -- ObjectKind=Sheet Symbol|PrimaryId=H1
      port
      (
        CLEAR  : in  STD_LOGIC;                              -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-CLEAR
        CLOCK  : in  STD_LOGIC;                              -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-CLOCK
        ENABLE : in  STD_LOGIC;                              -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-ENABLE
        OCD    : out STD_LOGIC_VECTOR(3 downto 0);           -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-OCD[3..0]
        RCO    : out STD_LOGIC                               -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-RCO
      );
   End Component;

   Component BUFGS                                           -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      port
      (
        I : in  STD_LOGIC;                                   -- ObjectKind=Pin|PrimaryId=U1-I
        O : out STD_LOGIC                                    -- ObjectKind=Pin|PrimaryId=U1-O
      );
   End Component;

   Component PARITYC                                         -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      port
      (
        L : in  STD_LOGIC_VECTOR(3 downto 0);                -- ObjectKind=Pin|PrimaryId=U2-L[3..0]
        P : out STD_LOGIC;                                   -- ObjectKind=Pin|PrimaryId=U2-P
        U : in  STD_LOGIC_VECTOR(3 downto 0)                 -- ObjectKind=Pin|PrimaryId=U2-U[3..0]
      );
   End Component;


    Signal PinSignal_H1_OCD  : STD_LOGIC_VECTOR(3 downto 0); -- ObjectKind=Net|PrimaryId=LOWER[3..0]
    Signal PinSignal_H1_RCO  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=LRCO
    Signal PinSignal_H2_OCD  : STD_LOGIC_VECTOR(3 downto 0); -- ObjectKind=Net|PrimaryId=S1[3..0]
    Signal PinSignal_H2_RCO  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=RCO
    Signal PinSignal_U1_O    : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O
    Signal PinSignal_U2_P    : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_P

begin
    H2 : BCD                                                 -- ObjectKind=Sheet Symbol|PrimaryId=H2
      Port Map
      (
        CLEAR  => CLEAR,                                     -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-CLEAR
        CLOCK  => PinSignal_U1_O,                            -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-CLOCK
        ENABLE => PinSignal_H1_RCO,                          -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-ENABLE
        OCD    => PinSignal_H2_OCD,                          -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-OCD[3..0]
        RCO    => PinSignal_H2_RCO                           -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-RCO
      );

    H1 : BCD                                                 -- ObjectKind=Sheet Symbol|PrimaryId=H1
      Port Map
      (
        CLEAR  => CLEAR,                                     -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-CLEAR
        CLOCK  => PinSignal_U1_O,                            -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-CLOCK
        ENABLE => ENABLE,                                    -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-ENABLE
        OCD    => PinSignal_H1_OCD,                          -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-OCD[3..0]
        RCO    => PinSignal_H1_RCO                           -- ObjectKind=Sheet Entry|PrimaryId=BCD.VHD-RCO
      );

    U2 : PARITYC                                             -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      Port Map
      (
        L => PinSignal_H1_OCD,                               -- ObjectKind=Pin|PrimaryId=U2-L[3..0]
        P => PinSignal_U2_P,                                 -- ObjectKind=Pin|PrimaryId=U2-P
        U => PinSignal_H2_OCD                                -- ObjectKind=Pin|PrimaryId=U2-U[3..0]
      );

    U1 : BUFGS                                               -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      Port Map
      (
        I => CLOCK,                                          -- ObjectKind=Pin|PrimaryId=U1-I
        O => PinSignal_U1_O                                  -- ObjectKind=Pin|PrimaryId=U1-O
      );

    -- Signal Assignments
    ---------------------
    LOWER  <= PinSignal_H1_OCD; -- ObjectKind=Net|PrimaryId=LOWER[3..0]
    PARITY <= PinSignal_U2_P; -- ObjectKind=Net|PrimaryId=NetU2_P
    UPPER  <= PinSignal_H2_OCD; -- ObjectKind=Net|PrimaryId=S1[3..0]
    URCO   <= PinSignal_H2_RCO; -- ObjectKind=Net|PrimaryId=RCO

end structure;
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