sheet1.vhd

altium designer09设计教程+原理图+PCB实例

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-- VHDL Sheet1
-- 2010 5 27 16 52 21
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL Sheet1
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Library IEEE;
Use     IEEE.std_logic_1164.all;

Entity FPGA_Project1 Is
  port
  (
    IN1 : In    STD_LOGIC;
    IN2 : In    STD_LOGIC;
    IN3 : Out   STD_LOGIC;
    IN4 : In    STD_LOGIC;
    IN5 : Out   STD_LOGIC
  );
  attribute MacroCell : boolean;

  attribute Part_name : string;
  attribute Part_name of FPGA_Project1 : Entity is "EPM7128";

  attribute PinNum : string;
  attribute PinNum of IN1 : Signal is "5";
  attribute PinNum of IN2 : Signal is "4";
  attribute PinNum of IN3 : Signal is "3";
  attribute PinNum of IN4 : Signal is "2";


End FPGA_Project1;
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architecture structure of FPGA_Project1 is
   Component SN74LS04D
      port
      (
        X_1  : in    STD_LOGIC;
        X_2  : out   STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_14 : inout STD_LOGIC
      );
   End Component;

   Component SN74LS08D
      port
      (
        X_1  : in    STD_LOGIC;
        X_2  : in    STD_LOGIC;
        X_3  : out   STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_14 : inout STD_LOGIC
      );
   End Component;

   Component SN74LS32D
      port
      (
        X_1  : in    STD_LOGIC;
        X_2  : in    STD_LOGIC;
        X_3  : out   STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_14 : inout STD_LOGIC
      );
   End Component;

   Component SN74LS173AD
      port
      (
        X_1  : in    STD_LOGIC;
        X_2  : in    STD_LOGIC;
        X_3  : inout STD_LOGIC;
        X_4  : inout STD_LOGIC;
        X_5  : inout STD_LOGIC;
        X_6  : inout STD_LOGIC;
        X_7  : in    STD_LOGIC;
        X_8  : inout STD_LOGIC;
        X_9  : in    STD_LOGIC;
        X_10 : in    STD_LOGIC;
        X_11 : in    STD_LOGIC;
        X_12 : in    STD_LOGIC;
        X_13 : in    STD_LOGIC;
        X_14 : in    STD_LOGIC;
        X_15 : in    STD_LOGIC;
        X_16 : inout STD_LOGIC
      );
   End Component;


    Signal PinSignal_U1_11 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_11
    Signal PinSignal_U1_3  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_3
    Signal PinSignal_U1_4  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_4
    Signal PinSignal_U1_6  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_6
    Signal PinSignal_U1_8  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_8
    Signal PinSignal_U1_9  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_9
    Signal PinSignal_U2_3  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_3
    Signal PinSignal_U2_6  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_6
    Signal PinSignal_U3_3  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_3
    Signal PinSignal_U3_6  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=H1
    Signal PinSignal_U3_8  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=H2
    Signal PinSignal_U4_2  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_2
    Signal PinSignal_U4_3  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU4_3
    Signal PinSignal_U4_4  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=H3
    Signal PinSignal_U4_6  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU4_6
    Signal PinSignal_U5_3  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU5_3
    Signal PinSignal_U5_6  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU5_6
    Signal PowerSignal_GND : STD_LOGIC; -- ObjectKind=Net|PrimaryId=GND
    Signal PowerSignal_VCC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC

   attribute Code_IPC : string;
   attribute Code_IPC of SN74LS04D   : Component is "SOIC127P600-14";
   attribute Code_IPC of SN74LS08D   : Component is "SOIC127P600-14";
   attribute Code_IPC of SN74LS32D   : Component is "SOIC127P600-14";
   attribute Code_IPC of SN74LS173AD : Component is "SOIC127P600-16";

   attribute DatasheetVersion : string;
   attribute DatasheetVersion of SN74LS04D   : Component is "Mar-1988";
   attribute DatasheetVersion of SN74LS08D   : Component is "Mar-1988";
   attribute DatasheetVersion of SN74LS32D   : Component is "Mar-1988";
   attribute DatasheetVersion of SN74LS173AD : Component is "Mar-1988";

   attribute PackageDescription : string;
   attribute PackageDescription of SN74LS04D   : Component is "14-Pin Small Outline Integrated Circuit 1.27 mm Pitch";
   attribute PackageDescription of SN74LS08D   : Component is "14-Pin Small Outline Integrated Circuit 1.27 mm Pitch";
   attribute PackageDescription of SN74LS32D   : Component is "14-Pin Small Outline Integrated Circuit 1.27 mm Pitch";
   attribute PackageDescription of SN74LS173AD : Component is "16-Pin Small Outline Integrated Circuit 1.27 mm Pitch";

   attribute PackageReference : string;
   attribute PackageReference of SN74LS04D   : Component is "D014";
   attribute PackageReference of SN74LS08D   : Component is "D014";
   attribute PackageReference of SN74LS32D   : Component is "D014";
   attribute PackageReference of SN74LS173AD : Component is "D016";

   attribute PackageVersion : string;
   attribute PackageVersion of SN74LS04D   : Component is "Jan-1998";
   attribute PackageVersion of SN74LS08D   : Component is "Jan-1998";
   attribute PackageVersion of SN74LS32D   : Component is "Jan-1998";
   attribute PackageVersion of SN74LS173AD : Component is "Jan-1998";




begin
    U5 : SN74LS173AD
      Port Map
      (
        X_1  => PinSignal_U3_6,
        X_2  => IN1,
        X_3  => PinSignal_U5_3,
        X_4  => PinSignal_U1_9,
        X_5  => PinSignal_U1_9,
        X_6  => PinSignal_U5_6,
        X_8  => PinSignal_U5_6,
        X_9  => IN1,
        X_10 => IN1,
        X_11 => IN1,
        X_12 => PinSignal_U3_8,
        X_14 => PinSignal_U4_4,
        X_15 => IN1,
        X_16 => PinSignal_U5_3
      );

    U4 : SN74LS04D
      Port Map
      (
        X_5 => PinSignal_U1_9,
        X_6 => PinSignal_U4_6
      );

    U4 : SN74LS04D
      Port Map
      (
        X_3 => PinSignal_U4_3,
        X_4 => PinSignal_U4_4
      );

    U4 : SN74LS04D
      Port Map
      (
        X_1  => PinSignal_U1_9,
        X_2  => PinSignal_U4_2,
        X_7  => PowerSignal_GND,
        X_14 => PowerSignal_VCC
      );

    U3 : SN74LS32D
      Port Map
      (
        X_8  => PinSignal_U3_8,
        X_9  => PinSignal_U3_3,
        X_10 => PinSignal_U2_6
      );

    U3 : SN74LS32D
      Port Map
      (
        X_4 => PinSignal_U1_3,
        X_5 => PinSignal_U1_6,
        X_6 => PinSignal_U3_6
      );

    U3 : SN74LS32D
      Port Map
      (
        X_1  => PinSignal_U1_8,
        X_2  => PinSignal_U1_11,
        X_3  => PinSignal_U3_3,
        X_7  => PowerSignal_GND,
        X_14 => PowerSignal_VCC
      );

    U2 : SN74LS08D
      Port Map
      (
        X_4 => PinSignal_U2_3,
        X_5 => IN4,
        X_6 => PinSignal_U2_6
      );

    U2 : SN74LS08D
      Port Map
      (
        X_1  => PinSignal_U4_4,
        X_2  => PinSignal_U4_2,
        X_3  => PinSignal_U2_3,
        X_7  => PowerSignal_GND,
        X_14 => PowerSignal_VCC
      );

    U1 : SN74LS08D
      Port Map
      (
        X_11 => PinSignal_U1_11,
        X_12 => PinSignal_U1_9,
        X_13 => PinSignal_U1_4
      );

    U1 : SN74LS08D
      Port Map
      (
        X_8  => PinSignal_U1_8,
        X_9  => PinSignal_U1_9,
        X_10 => PinSignal_U4_2
      );

    U1 : SN74LS08D
      Port Map
      (
        X_4 => PinSignal_U1_4,
        X_5 => IN2,
        X_6 => PinSignal_U1_6
      );

    U1 : SN74LS08D
      Port Map
      (
        X_1  => PinSignal_U4_4,
        X_2  => PinSignal_U4_2,
        X_3  => PinSignal_U1_3,
        X_7  => PowerSignal_GND,
        X_14 => PowerSignal_VCC
      );

    -- Signal Assignments
    ---------------------
    IN3             <= PinSignal_U4_3; -- ObjectKind=Net|PrimaryId=NetU4_3
    IN5             <= PinSignal_U4_6; -- ObjectKind=Net|PrimaryId=NetU4_6
    PinSignal_U4_3  <= IN3; -- ObjectKind=Net|PrimaryId=NetU4_3
    PowerSignal_GND <= '0'; -- ObjectKind=Net|PrimaryId=GND
    PowerSignal_VCC <= '1'; -- ObjectKind=Net|PrimaryId=VCC

end structure;
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