sheet1.vhd

altium designer09设计教程+原理图+PCB实例

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-- VHDL Sheet1
-- 2010 5 27 17 30 38
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL Sheet1
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Library IEEE;
Use     IEEE.std_logic_1164.all;

Entity FPGA_Project1 Is
  port
  (
    IN1 : In    STD_LOGIC;
    IN2 : In    STD_LOGIC;
    IN3 : In    STD_LOGIC;
    IN4 : In    STD_LOGIC;
    IN5 : Out   STD_LOGIC;
    IN6 : Out   STD_LOGIC;
    IN7 : Out   STD_LOGIC
  );
  attribute MacroCell : boolean;

  attribute Part_name : string;
  attribute Part_name of FPGA_Project1 : Entity is "EPM7128";

  attribute PinNum : string;
  attribute PinNum of IN1 : Signal is "1.2.3.4.5.";
  attribute PinNum of IN2 : Signal is "6";
  attribute PinNum of IN3 : Signal is "7";
  attribute PinNum of IN4 : Signal is "8";
  attribute PinNum of IN5 : Signal is "14";
  attribute PinNum of IN6 : Signal is "15";
  attribute PinNum of IN7 : Signal is "16";


End FPGA_Project1;
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architecture structure of FPGA_Project1 is
   Component X_54LS51DMQB
      port
      (
        X_1  : in    STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_8  : out   STD_LOGIC;
        X_9  : in    STD_LOGIC;
        X_10 : in    STD_LOGIC;
        X_11 : in    STD_LOGIC;
        X_12 : in    STD_LOGIC;
        X_13 : in    STD_LOGIC;
        X_14 : inout STD_LOGIC
      );
   End Component;

   Component X_74AC08PC
      port
      (
        X_1  : in    STD_LOGIC;
        X_2  : in    STD_LOGIC;
        X_3  : out   STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_14 : inout STD_LOGIC
      );
   End Component;

   Component X_74AC32MTC
      port
      (
        X_1  : in    STD_LOGIC;
        X_2  : in    STD_LOGIC;
        X_3  : out   STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_14 : inout STD_LOGIC
      );
   End Component;

   Component MC10E156FN
      port
      (
        X_1  : inout STD_LOGIC;
        X_2  : in    STD_LOGIC;
        X_3  : in    STD_LOGIC;
        X_4  : in    STD_LOGIC;
        X_5  : in    STD_LOGIC;
        X_6  : in    STD_LOGIC;
        X_7  : in    STD_LOGIC;
        X_8  : in    STD_LOGIC;
        X_9  : in    STD_LOGIC;
        X_10 : inout STD_LOGIC;
        X_11 : inout STD_LOGIC;
        X_12 : inout STD_LOGIC;
        X_13 : inout STD_LOGIC;
        X_14 : inout STD_LOGIC;
        X_15 : inout STD_LOGIC;
        X_16 : inout STD_LOGIC;
        X_17 : inout STD_LOGIC;
        X_18 : inout STD_LOGIC;
        X_19 : inout STD_LOGIC;
        X_20 : in    STD_LOGIC;
        X_21 : in    STD_LOGIC;
        X_22 : in    STD_LOGIC;
        X_23 : in    STD_LOGIC;
        X_24 : in    STD_LOGIC;
        X_25 : in    STD_LOGIC;
        X_26 : in    STD_LOGIC;
        X_27 : in    STD_LOGIC;
        X_28 : in    STD_LOGIC
      );
   End Component;


    Signal PinSignal_U1_8  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_8
    Signal PinSignal_U2_3  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_3
    Signal PinSignal_U2_6  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_6
    Signal PinSignal_U3_3  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_3
    Signal PinSignal_U3_6  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_6
    Signal PinSignal_U3_8  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_8
    Signal PinSignal_U5_14 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU5_14
    Signal PinSignal_U5_15 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU5_15
    Signal PowerSignal_GND : STD_LOGIC; -- ObjectKind=Net|PrimaryId=GND
    Signal PowerSignal_VCC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC

   attribute DatasheetVersion : string;
   attribute DatasheetVersion of X_54LS51DMQB : Component is "Mar-1998";
   attribute DatasheetVersion of X_74AC08PC   : Component is "Nov-1999";
   attribute DatasheetVersion of X_74AC32MTC  : Component is "Nov-1999";
   attribute DatasheetVersion of MC10E156FN   : Component is "1996";

   attribute PackageDescription : string;
   attribute PackageDescription of X_54LS51DMQB : Component is "DIP; 14 Leads; Row Spacing 7.62 mm; Pitch 2.54 mm";
   attribute PackageDescription of X_74AC08PC   : Component is "DIP; 14 Leads; Row Spacing 7.62 mm; Pitch 2.54 mm";
   attribute PackageDescription of X_74AC32MTC  : Component is "Shrink Small Outline; 14 Leads; Body Width 4.4 mm; Pitch 0.65 mm";
   attribute PackageDescription of MC10E156FN   : Component is "28-Pin Leaded Chip Carrier 1.27 mm Pitch";

   attribute PackageReference : string;
   attribute PackageReference of X_54LS51DMQB : Component is "J14A";
   attribute PackageReference of X_74AC08PC   : Component is "N14A";
   attribute PackageReference of X_74AC32MTC  : Component is "MTC14";
   attribute PackageReference of MC10E156FN   : Component is "776-02";

   attribute PackageVersion : string;
   attribute PackageVersion of X_54LS51DMQB : Component is "2000";
   attribute PackageVersion of X_74AC08PC   : Component is "2000";
   attribute PackageVersion of X_74AC32MTC  : Component is "Aug-1999";
   attribute PackageVersion of MC10E156FN   : Component is "Feb-2000";




begin
    U5 : MC10E156FN
      Port Map
      (
        X_1  => PinSignal_U3_8,
        X_9  => PinSignal_U3_6,
        X_14 => PinSignal_U5_14,
        X_15 => PinSignal_U5_15,
        X_23 => PinSignal_U3_8
      );

    U3 : X_74AC32MTC
      Port Map
      (
        X_8  => PinSignal_U3_8,
        X_9  => PinSignal_U3_3,
        X_10 => PinSignal_U3_3
      );

    U3 : X_74AC32MTC
      Port Map
      (
        X_4 => PinSignal_U2_3,
        X_5 => PinSignal_U2_6,
        X_6 => PinSignal_U3_6
      );

    U3 : X_74AC32MTC
      Port Map
      (
        X_1  => PinSignal_U2_6,
        X_2  => PinSignal_U1_8,
        X_3  => PinSignal_U3_3,
        X_7  => PowerSignal_GND,
        X_14 => PowerSignal_VCC
      );

    U2 : X_74AC08PC
      Port Map
      (
        X_4 => IN3,
        X_5 => PinSignal_U1_8,
        X_6 => PinSignal_U2_6
      );

    U2 : X_74AC08PC
      Port Map
      (
        X_1  => PinSignal_U1_8,
        X_2  => PinSignal_U1_8,
        X_3  => PinSignal_U2_3,
        X_7  => PowerSignal_GND,
        X_14 => PowerSignal_VCC
      );

    U1 : X_54LS51DMQB
      Port Map
      (
        X_7  => PowerSignal_GND,
        X_8  => PinSignal_U1_8,
        X_11 => IN2,
        X_14 => PowerSignal_VCC
      );

    -- Signal Assignments
    ---------------------
    IN5             <= PinSignal_U5_15; -- ObjectKind=Net|PrimaryId=NetU5_15
    IN6             <= PinSignal_U5_14; -- ObjectKind=Net|PrimaryId=NetU5_14
    PinSignal_U5_14 <= IN6; -- ObjectKind=Net|PrimaryId=NetU5_14
    PinSignal_U5_15 <= IN5; -- ObjectKind=Net|PrimaryId=NetU5_15
    PowerSignal_GND <= '0'; -- ObjectKind=Net|PrimaryId=GND
    PowerSignal_VCC <= '1'; -- ObjectKind=Net|PrimaryId=VCC

end structure;
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