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Info: Start Nativelink Simulation process Info: NativeLink has detected VHDL design -- VHDL simulation models will be used ========= EDA Simulation Settings ===================== Sim Mode

Info: Start Nativelink Simulation process Info: NativeLink has detected VHDL design -- VHDL simulation models will be used ========= EDA Simulation Settings ===================== Sim Mode

------------------------------------------------------------ -- VHDL CPU -- 2010 5 27 16 7 45 -- Created By "Altium Designer VHDL Generator" -- "Copyright (c) 2002-2004 Altium Limited" ----------

------------------------------------------------------------ -- VHDL CPU -- 2010 5 27 16 7 45 -- Created By "Altium Designer VHDL Generator" -- "Copyright (c) 2002-2004 Altium Limited" ----------

Info: Start Nativelink Simulation process Info: NativeLink has detected VHDL design -- VHDL simulation models will be used ========= EDA Simulation Settings ===================== Sim Mode

version 3 f:\vhdlproject\vhdl0716\narrow_wide_pulse_generate.vhd narrow_wide_pulse_generate VHDL VHDL test.xwv Clocked - - 20000000000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEG

version 3 miao.vhdl miao VHDL VHDL m59.xwv Clocked - - 20000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEGIN CLK 50000000 50000000 10000000 10000000 0 RISING CLOCK_LIST_END

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu