test.tbw

来自「ISE7.1」· TBW 代码 · 共 44 行

version 3
f:\vhdlproject\vhdl0716\narrow_wide_pulse_generate.vhd
narrow_wide_pulse_generate
VHDL
VHDL
test.xwv
Clocked
-
-
20000000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
50000000
50000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
narrow_wide_pulse
clk
reset
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
narrow_wide_pulse_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
reset
narrow_wide_pulse
SIGNAL_ORDER_END
-X-X-X-