cpu.vhd

altium designer09设计教程+原理图+PCB实例

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-- VHDL CPU
-- 2010 5 27 16 7 45
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL CPU
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Library IEEE;
Use     IEEE.std_logic_1164.all;

Entity FPGA_Project1 Is
  port
  (
    X_15      : UnDef STD_LOGIC;
    X_44      : UnDef STD_LOGIC;
    AUP       : UnDef STD_LOGIC;
    CLK       : UnDef STD_LOGIC;
    CLK10     : UnDef STD_LOGIC;
    CLK11     : UnDef STD_LOGIC;
    CLK12     : UnDef STD_LOGIC;
    CPU_A_BUS : UnDef STD_LOGIC;
    CPU_D_BUS : UnDef STD_LOGIC;
    INP0      : UnDef STD_LOGIC;
    INP1      : UnDef STD_LOGIC;
    IO_PPU_CE : UnDef STD_LOGIC;
    NMI       : UnDef STD_LOGIC;
    R_W       : UnDef STD_LOGIC;
    RDY       : UnDef STD_LOGIC
  );
  attribute MacroCell : boolean;

  attribute Part_name : string;
  attribute Part_name of FPGA_Project1 : Entity is "EPM7128";

  attribute PinNum : string;
  attribute PinNum of X_15      : Signal is "8";
  attribute PinNum of X_44      : Signal is "11";
  attribute PinNum of AUP       : Signal is "60";
  attribute PinNum of CLK       : Signal is "10";
  attribute PinNum of CLK10     : Signal is "1";
  attribute PinNum of CLK11     : Signal is "2";
  attribute PinNum of CLK12     : Signal is "3";
  attribute PinNum of CPU_A_BUS : Signal is "29";
  attribute PinNum of CPU_D_BUS : Signal is "13";
  attribute PinNum of INP0      : Signal is "4";
  attribute PinNum of INP1      : Signal is "5";
  attribute PinNum of IO_PPU_CE : Signal is "12";
  attribute PinNum of NMI       : Signal is "7";
  attribute PinNum of R_W       : Signal is "6";
  attribute PinNum of RDY       : Signal is "9";


End FPGA_Project1;
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architecture structure of FPGA_Project1 is
   Component X_6116
      port
      (
        X_1  : inout STD_LOGIC;
        X_2  : inout STD_LOGIC;
        X_3  : inout STD_LOGIC;
        X_4  : inout STD_LOGIC;
        X_5  : inout STD_LOGIC;
        X_6  : inout STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_8  : inout STD_LOGIC;
        X_9  : inout STD_LOGIC;
        X_10 : inout STD_LOGIC;
        X_11 : inout STD_LOGIC;
        X_12 : inout STD_LOGIC;
        X_13 : inout STD_LOGIC;
        X_14 : inout STD_LOGIC;
        X_15 : inout STD_LOGIC;
        X_16 : inout STD_LOGIC;
        X_17 : inout STD_LOGIC;
        X_18 : inout STD_LOGIC;
        X_19 : inout STD_LOGIC;
        X_20 : inout STD_LOGIC;
        X_21 : inout STD_LOGIC;
        X_22 : inout STD_LOGIC;
        X_23 : inout STD_LOGIC;
        X_24 : inout STD_LOGIC
      );
   End Component;

   Component X_6527P
      port
      (
        X_1  : inout STD_LOGIC;
        X_2  : inout STD_LOGIC;
        X_3  : inout STD_LOGIC;
        X_4  : inout STD_LOGIC;
        X_5  : inout STD_LOGIC;
        X_6  : inout STD_LOGIC;
        X_7  : inout STD_LOGIC;
        X_8  : inout STD_LOGIC;
        X_9  : inout STD_LOGIC;
        X_10 : inout STD_LOGIC;
        X_11 : inout STD_LOGIC;
        X_12 : inout STD_LOGIC;
        X_13 : inout STD_LOGIC;
        X_14 : inout STD_LOGIC;
        X_15 : inout STD_LOGIC;
        X_16 : inout STD_LOGIC;
        X_17 : inout STD_LOGIC;
        X_18 : inout STD_LOGIC;
        X_19 : inout STD_LOGIC;
        X_20 : inout STD_LOGIC;
        X_21 : inout STD_LOGIC;
        X_22 : inout STD_LOGIC;
        X_23 : inout STD_LOGIC;
        X_24 : inout STD_LOGIC;
        X_25 : inout STD_LOGIC;
        X_26 : inout STD_LOGIC;
        X_27 : inout STD_LOGIC;
        X_28 : inout STD_LOGIC;
        X_29 : inout STD_LOGIC;
        X_30 : inout STD_LOGIC;
        X_31 : inout STD_LOGIC;
        X_32 : inout STD_LOGIC;
        X_33 : inout STD_LOGIC;
        X_34 : inout STD_LOGIC;
        X_35 : inout STD_LOGIC;
        X_36 : inout STD_LOGIC;
        X_37 : inout STD_LOGIC;
        X_38 : inout STD_LOGIC;
        X_39 : inout STD_LOGIC;
        X_40 : inout STD_LOGIC
      );
   End Component;

   Component SN74LS139N
      port
      (
        X_1  : in    STD_LOGIC;
        X_2  : in    STD_LOGIC;
        X_3  : in    STD_LOGIC;
        X_4  : out   STD_LOGIC;
        X_5  : out   STD_LOGIC;
        X_6  : out   STD_LOGIC;
        X_7  : out   STD_LOGIC;
        X_8  : inout STD_LOGIC;
        X_16 : inout STD_LOGIC
      );
   End Component;


    Signal PinSignal_1          : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_1
    Signal PinSignal_21         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_21
    Signal PinSignal_29         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_29
    Signal PinSignal_31         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_31
    Signal PinSignal_32         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_32
    Signal PinSignal_33         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_33
    Signal PinSignal_35         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_35
    Signal PinSignal_36         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_36
    Signal PinSignal_37         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_37
    Signal PinSignal_38         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_38
    Signal PinSignal_39         : STD_LOGIC; -- ObjectKind=Net|PrimaryId=Net*_39
    Signal PinSignal_U1_11      : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_11
    Signal PinSignal_U1_12      : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU0_18
    Signal PinSignal_U1_5       : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_5
    Signal PinSignal_U1_7       : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_7
    Signal PowerSignal_GND      : STD_LOGIC; -- ObjectKind=Net|PrimaryId=GND
    Signal PowerSignal_VCC      : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC

   attribute Code_JEDEC : string;
   attribute Code_JEDEC of SN74LS139N : Component is "MS-001-BB";

   attribute DatasheetVersion : string;
   attribute DatasheetVersion of SN74LS139N : Component is "Dec-1999";

   attribute PackageDescription : string;
   attribute PackageDescription of SN74LS139N : Component is "DIP; 16 Leads; Row Spacing 7.62 mm; Pitch 2.54 mm";

   attribute PackageReference : string;
   attribute PackageReference of SN74LS139N : Component is "648-08";

   attribute PackageVersion : string;
   attribute PackageVersion of SN74LS139N : Component is "Apr-2000";




begin
    U1 : SN74LS139N
      Port Map
      (
        X_11 => PinSignal_U1_11,
        X_12 => PinSignal_U1_12,
        X_13 => PinSignal_U1_5,
        X_14 => PinSignal_U1_5,
        X_15 => PinSignal_U1_5
      );

    U1 : SN74LS139N
      Port Map
      (
        X_1  => PowerSignal_GND,
        X_5  => PinSignal_U1_5,
        X_7  => PinSignal_U1_7,
        X_8  => PowerSignal_GND,
        X_16 => PowerSignal_VCC
      );

    U0 : X_6116
      Port Map
      (
        X_18 => PinSignal_U1_12,
        X_21 => PinSignal_21
      );

    X : X_6527P
      Port Map
      (
        X_1  => PinSignal_1,
        X_20 => PowerSignal_GND,
        X_21 => PinSignal_21,
        X_22 => PinSignal_21,
        X_23 => PinSignal_21,
        X_24 => PinSignal_21,
        X_25 => PinSignal_21,
        X_26 => PinSignal_21,
        X_27 => PinSignal_21,
        X_28 => PinSignal_21,
        X_29 => PinSignal_29,
        X_31 => PinSignal_31,
        X_32 => PinSignal_32,
        X_33 => PinSignal_33,
        X_34 => PinSignal_21,
        X_35 => PinSignal_35,
        X_36 => PinSignal_36,
        X_37 => PinSignal_37,
        X_38 => PinSignal_38,
        X_39 => PinSignal_39
      );

    -- Signal Assignments
    ---------------------
    AUP             <= PinSignal_1; -- ObjectKind=Net|PrimaryId=Net*_1
    CLK             <= PinSignal_29; -- ObjectKind=Net|PrimaryId=Net*_29
    CLK10           <= PinSignal_39; -- ObjectKind=Net|PrimaryId=Net*_39
    CLK11           <= PinSignal_38; -- ObjectKind=Net|PrimaryId=Net*_38
    CLK12           <= PinSignal_37; -- ObjectKind=Net|PrimaryId=Net*_37
    INP0            <= PinSignal_36; -- ObjectKind=Net|PrimaryId=Net*_36
    INP1            <= PinSignal_35; -- ObjectKind=Net|PrimaryId=Net*_35
    IO_PPU_CE       <= PinSignal_U1_11; -- ObjectKind=Net|PrimaryId=NetU1_11
    NMI             <= PinSignal_33; -- ObjectKind=Net|PrimaryId=Net*_33
    PinSignal_1     <= AUP; -- ObjectKind=Net|PrimaryId=Net*_1
    PinSignal_21    <= R_W; -- ObjectKind=Net|PrimaryId=Net*_21
    PinSignal_29    <= CLK; -- ObjectKind=Net|PrimaryId=Net*_29
    PinSignal_31    <= RDY; -- ObjectKind=Net|PrimaryId=Net*_31
    PinSignal_32    <= X_15; -- ObjectKind=Net|PrimaryId=Net*_32
    PinSignal_33    <= NMI; -- ObjectKind=Net|PrimaryId=Net*_33
    PinSignal_35    <= INP1; -- ObjectKind=Net|PrimaryId=Net*_35
    PinSignal_36    <= INP0; -- ObjectKind=Net|PrimaryId=Net*_36
    PinSignal_37    <= CLK12; -- ObjectKind=Net|PrimaryId=Net*_37
    PinSignal_38    <= CLK11; -- ObjectKind=Net|PrimaryId=Net*_38
    PinSignal_39    <= CLK10; -- ObjectKind=Net|PrimaryId=Net*_39
    PowerSignal_GND <= '0'; -- ObjectKind=Net|PrimaryId=GND
    PowerSignal_VCC <= '1'; -- ObjectKind=Net|PrimaryId=VCC
    R_W             <= PinSignal_21; -- ObjectKind=Net|PrimaryId=Net*_21
    RDY             <= PinSignal_31; -- ObjectKind=Net|PrimaryId=Net*_31
    X_15            <= PinSignal_32; -- ObjectKind=Net|PrimaryId=Net*_32
    X_44            <= PinSignal_U1_7; -- ObjectKind=Net|PrimaryId=NetU1_7

end structure;
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