代码搜索结果

# Caution: this file may be regenerated by SOPC Builder. User edits will be lost. project_open -current_revision "C:/altera/Hengdun/LED/LED.qpf" set_global_assignment -name VHDL_FILE altera_europa_

readme - Standard Design Overview: This design is provided for all Nios development boards and highlights many of the standard features of the Nios II processor. Contents of the System:

readme - Standard Design Overview: This design is provided for all Nios development boards and highlights many of the standard features of the Nios II processor. Contents of the System:

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

readme - Standard Design Overview: This design is provided for all Nios development boards and highlights many of the standard features of the Nios II processor. Contents of the System: - Nios

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

@N:"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":4:7:4:16|Synthesizing work.add_full_n.arch_add_full_n @W: CD280 :"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":14:10:14:17|Unbound component add_full m

set process "5" set part "2s200pq208" set tristate_map "TRUE" set opt_auto_mode "TRUE" set opt_best_result "29223.458000" set dont_lock_lcells "auto" set input2output "30.000000" set input2register "2

set process "5" set part "2s200pq208" set tristate_map "TRUE" set opt_auto_mode "TRUE" set opt_best_result "29223.458000" set dont_lock_lcells "auto" set input2output "30.000000" set input2register "2

/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2