inter.qsf

cpld

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		Inter_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF SMART
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:49:03  MAY 05, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 4.2
set_global_assignment -name BDF_FILE inter.bdf
set_global_assignment -name VHDL_FILE types.vhd
set_global_assignment -name VHDL_FILE functions.vhd
set_global_assignment -name VHDL_FILE Send_CMD_7279A.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE Inter.vwf
set_global_assignment -name VHDL_FILE perictr.vhd
set_global_assignment -name VHDL_FILE ReadKeyValBlock.vhd
set_global_assignment -name VHDL_FILE LCD_Display.vhd
set_global_assignment -name CDF_FILE Inter.cdf
set_global_assignment -name VHDL_FILE CLK_DIV.vhd
set_global_assignment -name VHDL_FILE altdpram0.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_89 -to CPLD_GCLRN
set_location_assignment PIN_94 -to DATA_IO[6]
set_location_assignment PIN_96 -to DATA_IO[7]
set_location_assignment PIN_8 -to DSP_DS
set_location_assignment PIN_16 -to HOLD
set_location_assignment PIN_17 -to BIO
set_location_assignment PIN_19 -to FPS_A0
set_location_assignment PIN_20 -to CS_FPS
set_location_assignment PIN_21 -to FPS_RD
set_location_assignment PIN_22 -to FPS_WR
set_location_assignment PIN_23 -to FPS_WAIT
set_location_assignment PIN_24 -to FPS_INTR
set_location_assignment PIN_25 -to FPS_EXINT
set_location_assignment PIN_27 -to BCLKR2
set_location_assignment PIN_28 -to BFSR2
set_location_assignment PIN_29 -to BDR2
set_location_assignment PIN_30 -to BCLKX2
set_location_assignment PIN_31 -to BFSX2
set_location_assignment PIN_35 -to BDX2
set_location_assignment PIN_44 -to FLASH_WR
set_location_assignment PIN_45 -to FLASH_A15
set_location_assignment PIN_46 -to FLASH_A17
set_location_assignment PIN_47 -to FLASH_RS
set_location_assignment PIN_48 -to FLASH_RY
set_location_assignment PIN_49 -to CSROM
set_location_assignment PIN_50 -to FLASH_RD
set_location_assignment PIN_52 -to FLASH_BYTE
set_location_assignment PIN_54 -to FLASH_A16
set_location_assignment PIN_58 -to DATA_IO[0]
set_location_assignment PIN_60 -to DATA_IO[1]
set_location_assignment PIN_61 -to DATA_IO[2]
set_location_assignment PIN_63 -to DATA_IO[3]
set_location_assignment PIN_64 -to DATA_IO[4]
set_location_assignment PIN_67 -to DATA_IO[5]
set_location_assignment PIN_68 -to A16
set_location_assignment PIN_69 -to A17
set_location_assignment PIN_70 -to A18
set_location_assignment PIN_71 -to CSRAM
set_location_assignment PIN_88 -to CPLD_OE1
set_location_assignment PIN_97 -to HD4
set_location_assignment PIN_98 -to HD5
set_location_assignment PIN_100 -to HD6
set_location_assignment PIN_1 -to PB_RS
set_location_assignment PIN_2 -to HD7
set_location_assignment PIN_6 -to DSP_READY
set_location_assignment PIN_7 -to DSP_PS
set_location_assignment PIN_9 -to DSP_IS
set_location_assignment PIN_10 -to DSP_RW
set_location_assignment PIN_12 -to DSP_MSTRB
set_location_assignment PIN_13 -to IOSTRB
set_location_assignment PIN_14 -to XF
set_location_assignment PIN_32 -to HD0
set_location_assignment PIN_36 -to NMI
set_location_assignment PIN_37 -to INT1
set_location_assignment PIN_40 -to DSP_Write_INT2
set_location_assignment PIN_41 -to INT3
set_location_assignment PIN_42 -to HD1
set_location_assignment PIN_55 -to HD2
set_location_assignment PIN_56 -to HD3
set_location_assignment PIN_57 -to RS
set_location_assignment PIN_75 -to Key
set_location_assignment PIN_79 -to Key_SDAT
set_location_assignment PIN_77 -to Key_CS
set_location_assignment PIN_72 -to Key_RESET
set_location_assignment PIN_90 -to CPLD_CLKIN
set_location_assignment PIN_87 -to CPLD_TOUT
set_location_assignment PIN_80 -to LCD_CS1
set_location_assignment PIN_81 -to LCD_CS2
set_location_assignment PIN_83 -to LCD_E
set_location_assignment PIN_84 -to LCD_RS
set_location_assignment PIN_85 -to LCD_RW
set_location_assignment PIN_76 -to Key_CLKOUT
set_location_assignment PIN_92 -to A19
set_location_assignment PIN_93 -to A20
set_location_assignment PIN_99 -to A0
set_location_assignment PIN_5 -to A15

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL Custom
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name TOP_LEVEL_ENTITY Inter

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM3128ATC100-10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
set_global_assignment -name GLITCH_INTERVAL 1

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_LMF_FILE mnt8_bas.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------

# --------------------------------------------
# start EDA_TOOL_SETTINGS(eda_timing_analysis)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_timing_analysis
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis

# end EDA_TOOL_SETTINGS(eda_timing_analysis)
# ------------------------------------------