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# VHDL : PDCL (jhdparse) __projnav/pn_correlation_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/fifo_status_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/pn_correlation_fsm_jhdparse_t

# VHDL : PDCL (jhdparse) __projnav/pn_correlation_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/fifo_status_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/pn_correlation_fsm_jhdparse_t

-proj f:\vhdl\shuzizhong\shuzizhong -t maintwb.tbw -source main.vhdl -entity topclock -ipcport 4984

vhdl isim_temp "baud_gen.vhd" vhdl isim_temp "baud_gen_test.vhd"

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VHDL proc_utils_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_utils_v1_00_a/hdl/vhdl/conv_funs_pkg.vhd VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl

VHDL proc_utils_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_utils_v1_00_a/hdl/vhdl/conv_funs_pkg.vhd VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl

config high_speed_ram; design project1_lib.high_speed_ram:sim_sch_1; liblist project1_lib, standard, classlib; viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, v

/bram_block_a.vhdl/1.1.1.1/Tue Dec 6 02:48:32 2005// /bram_block_b.vhdl/1.1.1.1/Tue Dec 6 02:48:32 2005// /counter2bit.vhdl/1.1.1.1/Tue Dec 6 02:48:32 2005// /folded_register.vhdl/1.1.1.1/Tue De

# VHDL : PDCL (jhdparse) __projnav/BIN_ADD_4BIT_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/COMPL