opb_wrapper_xst.prj

本系统由服务器软件控制平台和fpga硬件处理系统组成

VHDL proc_utils_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_utils_v1_00_a/hdl/vhdl/conv_funs_pkg.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/family.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/coregen_comp_defs.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/common_types_pkg.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/conv_funs_pkg.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/addsub.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/counter.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/direct_path_cntr.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/down_counter.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/eval_timer.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/ld_arith_reg2.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/or_bits.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/or_gate.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pselect.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/pselect_mask.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/srl_fifo.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/srl_fifo_rbu.vhd
VHDL proc_common_v2_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a/hdl/vhdl/valid_be.vhd
VHDL interrupt_control_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd
VHDL wrpfifo_v1_01_b g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd
VHDL wrpfifo_v1_01_b g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd
VHDL wrpfifo_v1_01_b g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd
VHDL wrpfifo_v1_01_b g:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd
VHDL rdpfifo_v1_01_b g:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd
VHDL rdpfifo_v1_01_b g:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd
VHDL rdpfifo_v1_01_b g:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/reset_mir.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/opb_flex_addr_cntr.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr_reg.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/opb_be_gen.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/srl_fifo3.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/write_buffer.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd
VHDL opb_ipif_v3_01_a g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a/hdl/vhdl/opb_ipif.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/opb_arb_pkg.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/or_muxcy.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/mux_onehot.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/or_bits.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/priority_reg.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/onehot2encoded.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/arbitration_logic.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/watchdog_timer.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/arb2bus_data_mux.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/control_register_logic.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/ipif_regonly_slave.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/priority_register_logic.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/opb_arbiter_core.vhd
VHDL opb_arbiter_v1_02_e g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_arbiter_v1_02_e/hdl/vhdl/opb_arbiter.vhd
VHDL opb_v20_v1_10_c g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c/hdl/vhdl/opb_v20.vhd
vhdl work ../hdl/opb_wrapper.vhd