expand.cfg

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config high_speed_ram;
design project1_lib.high_speed_ram:sim_sch_1;
liblist project1_lib, standard, classlib;
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch, pic_1, picopt_1, sim_sch_1, sch_1;
stoplist none;
endconfig