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# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

m255 o dD:\Projects\altera\lpcores\ddr\release\VHDL\V1_0\simulation Ealtcam DP std textio K]Z^fghZ6B=BjnK5NomDT3 DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:A

quit -sim cd D:/Verilog_VHDL/CH02/VHDL/Full_Adder --do run.do vlib work vmap work work vcom pkg_Full_Adder.vhd vcom Full_Adder.vhd vcom tb_Full_Adder.vhd vsim tb_Full_Adder --add wave

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

-- ***************************************************************** -- Specman Elite VHDL stubs file: specman_nc.vhd -- Topmost e module: -- Generated using seed = 1 -- Date: Mon Jun 14 09:27:31 200

; ; MTI script for analysis of ; reg_file_32_8_6port ; into register_file library ; ; set reg_file_vhdl R:\webs\model_9807 ; set reg_file_tools R:\webs\model_9807 ; do $reg_file_tools\reg_fi

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Tue Nov 01 21:08:53 2005 Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synplic