second.tcl

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II: Generate Tcl File for Project
# File: second.tcl
# Generated on: Sun Oct 05 20:06:52 2008

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "second"]} {
		puts "Project second is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists second]} {
		project_open -cmp second second
	} else {
		project_new -cmp second second
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	catch { set_global_assignment -name FAMILY Cyclone } result
	catch { set_global_assignment -name DEVICE EP1C3T144C8 } result
	catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2 } result
	catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:17:55  OCTOBER 05, 2008" } result
	catch { set_global_assignment -name LAST_QUARTUS_VERSION 7.2 } result
	catch { set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace } result
	catch { set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "ViewDraw (Symbol)" } result
	catch { set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "F:/FPGA_CHENGXU/MIAOBIAO/fenpin" -section_id eda_board_design_symbol } result
	catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VIEWDRAW -section_id eda_board_design_symbol } result
	catch { set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP } result
	catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 } result
	catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 } result
	catch { set_global_assignment -name BDF_FILE second.bdf } result
	catch { set_global_assignment -name VHDL_FILE fenpin.vhd } result
	catch { set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top } result
	catch { set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top } result
	catch { set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" } result
	catch { set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" } result
	catch { set_global_assignment -name VHDL_FILE cnt_10.vhd } result
	catch { set_global_assignment -name VHDL_FILE xian.vhd } result
	catch { set_global_assignment -name VHDL_FILE cnt_12.vhd } result
	catch { set_global_assignment -name VHDL_FILE cnt_60.vhd } result
	catch { set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top } result
	catch { set_location_assignment PIN_93 -to clkin } result
	catch { set_location_assignment PIN_60 -to clr } result
	catch { set_location_assignment PIN_67 -to reset } result
	catch { set_location_assignment PIN_131 -to data[0] } result
	catch { set_location_assignment PIN_130 -to data[1] } result

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}