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# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

include libs_mi35.dc update_lib MTC45000 ramlib_mi35.lib read -format vhdl {"clkgen.vhd"} read -format vhdl {"iu.vhd"} group -hdl_all_blocks read -format vhdl {"regfile.vhd"} read -format vhd

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

V2 61 FL F:/vhdlproject/vhdl0716/top_fmdm_project.vhd 2007/07/23.21:53:48 H.42 EN work/TOP_FMDM_PROJECT 1185244012 FL F:/vhdlproject/vhdl0716/top_fmdm_project.vhd \ PB ieee/STD_LOGIC_1164 110

Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= *

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Wed Dec 20 13:47:13 中国标准时间 2006 ## vlib work vcom -93 -explicit counter10.vhdl vcom -93 -explicit counter.vhdl vc

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pmath_complex DP work math_real zjAF7SKfg_RPI0GT^n1N`1 OL;C;6.2b;35 31 b1 M1 work math_real OP;C;6.2b;35 d. F$MODEL_