代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/351504/10644977

log coregen.log

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log # busformat=BusFormatAn
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www.eeworm.com/read/277196/10655166

log coregen.log

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log # busformat=BusFormatAn
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www.eeworm.com/read/417505/10987319

mti end sem.cr.mti

{D:/niran/vhdl/end sem/adder_full.vhd} {2 {vcom -work ieee -2002 {D:/niran/vhdl/end sem/adder_full.vhd} ** Warning: (vcom-14) Failed to open "D:/niran/vhdl/end sem/end sem.mpf" specified by the MODEL
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www.eeworm.com/read/470494/6912175

qmsg add1.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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www.eeworm.com/read/469272/6979868

qmsg ledwater.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
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www.eeworm.com/read/467448/7012792

prj proj1.prj

#-- Synplicity, Inc. #-- Version 9.0 #-- Project file G:\eda\qdds\proj1.prj #-- Written on Sat Jul 19 16:47:32 2008 #add_file options add_file -vhdl -lib work "adder.vhd" add_file -vhdl -lib
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www.eeworm.com/read/467448/7012826

txt run_options.txt

#-- Synplicity, Inc. #-- Version 9.0 #-- Project file G:\eda\qdds\rev_1\run_options.txt #-- Written on Sat Jul 19 16:07:05 2008 #add_file options add_file -vhdl -lib work "adder.vhd" add_fil
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www.eeworm.com/read/465358/7053734

log coregen.log

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log # busformat=BusFormatAn
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www.eeworm.com/read/170130/7102928

npl lab4.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT lab4 DESIGN lab4 DEVFAM spartan2 DEVFAMTIME 0 DEVICE xc2s50 DEVICETIME 0 DEVPKG tq144 DEVPKGTIME 0 DEVSPEED -5 DEVSPEEDTIME 0 DEVTOPLE
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www.eeworm.com/read/170130/7102953

npl lab3.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT lab3 DESIGN lab3 DEVFAM spartan2 DEVFAMTIME 0 DEVICE xc2s50 DEVICETIME 0 DEVPKG tq144 DEVPKGTIME 0 DEVSPEED -5 DEVSPEEDTIME 0 DEVTOPLE
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