add1.map.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 22 13:57:28 2006 " "Info: Processing started: Wed Feb 22 13:57:28 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off add1 -c add1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off add1 -c add1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add1-doing " "Info: Found design unit 1: add1-doing" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 add1 " "Info: Found entity 1: add1" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "C:/altera/quartus50/333/Block1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "add1 " "Info: Elaborating entity \"add1\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a add1.vhd(50) " "Warning: VHDL Process Statement warning at add1.vhd(50): signal \"a\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b_data add1.vhd(50) " "Warning: VHDL Process Statement warning at add1.vhd(50): signal \"b_data\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "r add1.vhd(50) " "Warning: VHDL Process Statement warning at add1.vhd(50): signal \"r\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "add1.vhd" "" { Text "C:/altera/quartus50/333/add1.vhd" 50 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "54 " "Info: Implemented 54 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "20 " "Info: Implemented 20 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 22 13:57:31 2006 " "Info: Processing ended: Wed Feb 22 13:57:31 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}