run_options.txt

多功能函数发生器

#-- Synplicity, Inc.
#-- Version 9.0
#-- Project file G:\eda\qdds\rev_1\run_options.txt
#-- Written on Sat Jul 19 16:07:05 2008


#add_file options
add_file -vhdl -lib work "adder.vhd"
add_file -vhdl -lib work "d_switch.vhd"
add_file -vhdl -lib work "data_f.vhd"
add_file -vhdl -lib work "data_juchi.vhd"
add_file -vhdl -lib work "data_sin.vhd"
add_file -vhdl -lib work "data_v.vhd"
add_file -vhdl -lib work "dds.vhd"


#implementation: "rev_1"
impl -add rev_1 -type fpga

#device options
set_option -technology 500K
set_option -part A500K050

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1

#map options
set_option -frequency auto
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond Default
set_option -update_models_cp 0
set_option -preserve_registers 0


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "rev_1/dds.edn"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "rev_1"