ledwater.fit.qmsg

使用VHDL语言编写的跑马灯程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 09 10:20:03 2008 " "Info: Processing started: Wed Jul 09 10:20:03 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ledwater -c ledwater " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ledwater -c ledwater" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ledwater EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"ledwater\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 152 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 152" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 11 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted signal \"rst\" to use Global clock" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 12 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "" { rst } "NODE_NAME" } "" } } { "D:/程序VHDL--邓博/跑马灯/ledwater.fld" "" { Floorplan "D:/程序VHDL--邓博/跑马灯/ledwater.fld" "" "" { rst } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.323 ns register register " "Info: Estimated most critical path is register to register delay of 4.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LAB_X11_Y4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y4; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "" { cnt[0] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.292 ns) 0.740 ns reduce_nor~175 2 COMB LAB_X11_Y4 1 " "Info: 2: + IC(0.448 ns) + CELL(0.292 ns) = 0.740 ns; Loc. = LAB_X11_Y4; Fanout = 1; COMB Node = 'reduce_nor~175'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "0.740 ns" { cnt[0] reduce_nor~175 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.590 ns) 2.130 ns reduce_nor~177 3 COMB LAB_X12_Y2 1 " "Info: 3: + IC(0.800 ns) + CELL(0.590 ns) = 2.130 ns; Loc. = LAB_X12_Y2; Fanout = 1; COMB Node = 'reduce_nor~177'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.390 ns" { reduce_nor~175 reduce_nor~177 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 2.794 ns reduce_nor~0 4 COMB LAB_X12_Y2 12 " "Info: 4: + IC(0.074 ns) + CELL(0.590 ns) = 2.794 ns; Loc. = LAB_X12_Y2; Fanout = 12; COMB Node = 'reduce_nor~0'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "0.664 ns" { reduce_nor~177 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.662 ns) + CELL(0.867 ns) 4.323 ns dataout_tmp\[2\] 5 REG LAB_X13_Y2 2 " "Info: 5: + IC(0.662 ns) + CELL(0.867 ns) = 4.323 ns; Loc. = LAB_X13_Y2; Fanout = 2; REG Node = 'dataout_tmp\[2\]'" {  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "1.529 ns" { reduce_nor~0 dataout_tmp[2] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "D:/程序VHDL--邓博/跑马灯/ledwater.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.339 ns 54.11 % " "Info: Total cell delay = 2.339 ns ( 54.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.984 ns 45.89 % " "Info: Total interconnect delay = 1.984 ns ( 45.89 % )" {  } {  } 0}  } { { "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" "" { Report "D:/程序VHDL--邓博/跑马灯/db/ledwater_cmp.qrpt" Compiler "ledwater" "UNKNOWN" "V1" "D:/程序VHDL--邓博/跑马灯/db/ledwater.quartus_db" { Floorplan "D:/程序VHDL--邓博/跑马灯/" "" "4.323 ns" { cnt[0] reduce_nor~175 reduce_nor~177 reduce_nor~0 dataout_tmp[2] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 09 10:20:09 2008 " "Info: Processing ended: Wed Jul 09 10:20:09 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}