代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/461789/7219861

par_nlf led.par_nlf

Release 7.1.04i - netgen H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim led.nga led_timesim.vhd Reading d
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www.eeworm.com/read/461789/7219869

nlf led_timesim.nlf

Release 7.1.04i - netgen H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim led.nga led_timesim.vhd Reading d
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www.eeworm.com/read/461652/7222757

npl ofdm.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT ofdm DESIGN ofdm DEVFAM spartan2 DEVFAMTIME 1145426085 DEVICE xc2s200 DEVICETIME 1145426085 DEVPKG pq208 DEVPKGTIME 1145425004 DEVSPEED -5 DEVSPEE
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www.eeworm.com/read/454372/7393019

qmsg rom.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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www.eeworm.com/read/453446/7420390

mgf mux21.mgf

01000042 V MUX 5 ".\src\VHDL code7.vhd" 418 202 0 12 0 12 00000001 1 .\src\VHDL*code7.vhd 0 0 0 0 0 0 0 1 1 29 0 29 12 ~ ~ 0 0 0 67 0 1 15 ieee std_logic_1164 4 2 0 15 ieee std_logic_1164 0 0 0 0 1 29
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www.eeworm.com/read/453028/7427878

qsf tdma.qsf

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/448006/7542028

log coregen.log

# Xilinx CORE Generator 6.3i # User = Administrator Initializing default project... Loading plug-ins... All runtime messages will be recorded in G:\vijay_FPGA_LAB\bcd_7seg\coregen.log # busformat
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www.eeworm.com/read/448004/7542062

prj divd10.prj

vhdl work F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd
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www.eeworm.com/read/447996/7542465

log coregen.log

# Xilinx CORE Generator 6.3i # User = Administrator Initializing default project... Loading plug-ins... All runtime messages will be recorded in G:\vijay_FPGA_LAB\alu_2bit\coregen.log NEWPROJECT
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www.eeworm.com/read/447390/7553640

gfl fenpin.gfl

# ModelSim : Launch ModelSim Simulator fenpin1.ldo # ModelSim : Launch ModelSim Simulator vsim.wlf # ModelSim : Launch ModelSim Simulator fenpin1.ldo # ModelSim : Launch ModelSim Simulator vsim
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