rom.map.qmsg

基于ROM的正弦波发生器的设计:使用MATLAB得到这64个波形数据

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 19 09:47:09 2008 " "Info: Processing started: Sat Jan 19 09:47:09 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rom -c rom --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rom -c rom --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.vhd 8 4 " "Info: Found 8 design units, including 4 entities, in source file rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter " "Info: Found design unit 1: counter-counter" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 21 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 lock-beha " "Info: Found design unit 2: lock-beha" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 rom_1-rom " "Info: Found design unit 3: rom_1-rom" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 68 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 rom-structural " "Info: Found design unit 4: rom-structural" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 142 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rom " "Info: Found entity 1: rom" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 3 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 counter " "Info: Found entity 2: counter" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 lock " "Info: Found entity 3: lock" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 39 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 rom_1 " "Info: Found entity 4: rom_1" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 62 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rom " "Info: Elaborating entity \"rom\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:u0 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:u0\"" {  } { { "rom.vhd" "u0" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 165 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_1 rom_1:u1 " "Info: Elaborating entity \"rom_1\" for hierarchy \"rom_1:u1\"" {  } { { "rom.vhd" "u1" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 166 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lock lock:u2 " "Info: Elaborating entity \"lock\" for hierarchy \"lock:u2\"" {  } { { "rom.vhd" "u2" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 167 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "indata rom.vhd(52) " "Warning: VHDL Process Statement warning at rom.vhd(52): signal \"indata\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "rom.vhd" "" { Text "D:/课件/3-1/vhdl/experiment_7/rom.vhd" 52 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_qlc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_qlc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_qlc " "Info: Found entity 1: mux_qlc" {  } { { "db/mux_qlc.tdf" "" { Text "D:/课件/3-1/vhdl/experiment_7/db/mux_qlc.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_74i.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_74i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_74i " "Info: Found entity 1: add_sub_74i" {  } { { "db/add_sub_74i.tdf" "" { Text "D:/课件/3-1/vhdl/experiment_7/db/add_sub_74i.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 19 09:47:15 2008 " "Info: Processing ended: Sat Jan 19 09:47:15 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}