fenpin.gfl

此为EDA设计的分频器模块。可以实现三种不同的频率信号

# ModelSim : Launch ModelSim Simulator
fenpin1.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
fenpin1.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ProjNav -> New Source -> TBW
F:\fenpin\__projnav\hb_cmds
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_tbw_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_tbw_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
fenpin1_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
F:\dianzijishushiyan-dodo\fenpin\__projnav\hb_cmds
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
fenpin1.spl
__projnav/vhd2spl.err
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wave.vhw
wave.ano
wave.tfw
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
F:\dianzijishushiyan-dodo\fenpin\__projnav\hb_cmds
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf