代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/131754/14131428

npl i2c.npl

JDF F // Created by Project Navigator ver 1.0 PROJECT Untitled DESIGN i2c Normal DEVFAM xpla3 DEVFAMTIME 1039799570 DEVICE xcr3256xl DEVICETIME 1039799570 DEVPKG TQ144 DEVPKGTIME 315558000 D
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www.eeworm.com/read/233765/14137057

entityimport nco_v7_1_import.entityimport

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www.eeworm.com/read/232914/14178140

qmsg elec_lock.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/129810/14225380

rpt downclk.rpt

Project Informationd:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\downclk.rpt MAX+plus II Compiler Report File Version 10.12 09/21/2001 Compiled: 12/08/2003 13:16:03 Copyright (C) 1988-2001
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www.eeworm.com/read/230485/14285321

udo test.udo

-- ProjNav VHDL simulation template: test.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/127647/14345953

log coregen.log

# Xilinx CORE Generator 6.1i # User = gaolig Initializing default project... Loading plug-ins... All runtime messages will be recorded in H:\file\通信ASIC课程设计\pn_code\coregen.log # busformat=BusFor
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www.eeworm.com/read/227218/14436908

out anal.out

E:/vhdl_tools/100Examples/1_ADDER/1_ADDER.VHD: pout
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www.eeworm.com/read/227218/14436915

out anal.out

E:/vhdl_tools/100Examples/2_ADDER/2_ADDER.VHD: pout
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www.eeworm.com/read/223119/14656005

lst netlist.lst

E:\Cindy\working\UE_EXTBOARD\SP3\VHDL\PS2\ps2.ngc 1140592068 OK
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www.eeworm.com/read/223116/14656060

cmd_log vga.cmd_log

xst -intstyle ise -ifn __projnav/vga.xst -ofn vga.syr ngdbuild -dd _ngo -uc vga.ucf -p xc9500xl vga.ngc vga.ngd cpldfit -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -
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